commit b39236b6a071483f76db5bc3b89448c23c900b18
author Simon Pilgrim <llvm-dev@redking.me.uk> Fri Jul 29 18:57:32 2016 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Fri Jul 29 18:57:32 2016 +0000
tree 02c5d473b2a17ee1a2c29f6c8caf9a908a77d2c1
parent 718da3d1f6976a1bf89f960519ddab1316637c9a

Fixed (incorrectly firing) MSVC unused variable warning

llvm-svn: 277198

llvm/lib/CodeGen/MachinePipeliner.cpp

diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index ca74686..a4afdc94 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3819,7 +3819,6 @@
 // different stage than the definition. The pipeliner does not handle
 // physical register values that may cross a basic block boundary.
 bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {
-  const TargetRegisterInfo *TRI = ST.getRegisterInfo();
   for (int i = 0, e = SSD->SUnits.size(); i < e; ++i) {
     SUnit &SU = SSD->SUnits[i];
     if (!SU.hasPhysRegDefs)
@@ -3828,7 +3827,7 @@
     assert(StageDef != -1 && "Instruction should have been scheduled.");
     for (auto &SI : SU.Succs)
       if (SI.isAssignedRegDep())
-        if (TRI->isPhysicalRegister(SI.getReg()))
+        if (ST.getRegisterInfo()->isPhysicalRegister(SI.getReg()))
           if (stageScheduled(SI.getSUnit()) != StageDef)
             return false;
   }