commit b3a0be4d38ab08456aa4406e86d1b6c76581245a
author Tim Northover <tnorthover@apple.com> Tue Aug 23 21:01:20 2016 +0000
committer Tim Northover <tnorthover@apple.com> Tue Aug 23 21:01:20 2016 +0000
tree 90e8ec3f034084c4cb4a751d82888924d728cc89
parent 4c1f1f120c9da460a7b1d1f24936499d8caeae11

GlobalISel: legalize conditional branches on AArch64.

llvm-svn: 279565

llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
index bd8374c..f22cf35 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -173,6 +173,13 @@
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_BRCOND: {
+    unsigned TstExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildAnyExtend(WideTy, TstExt, MI.getOperand(0).getReg());
+    MIRBuilder.buildBrCond(WideTy, TstExt, *MI.getOperand(1).getMBB());
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }