[AArch64] Optimize floating point materialization
This patch changes isFPImmLegal to return if the value can be enconded
as the immediate operand of a logical instruction besides checking if
for immediate field for fmov.
This optimizes some floating point materization, inclusive values
used on isinf lowering.
Reviewed By: rengolin, efriedma, evandro
Differential Revision: https://reviews.llvm.org/D57044
llvm-svn: 352866
diff --git a/llvm/test/CodeGen/AArch64/win_cst_pool.ll b/llvm/test/CodeGen/AArch64/win_cst_pool.ll
index 5bcc919..f26e7aa 100644
--- a/llvm/test/CodeGen/AArch64/win_cst_pool.ll
+++ b/llvm/test/CodeGen/AArch64/win_cst_pool.ll
@@ -2,22 +2,22 @@
; RUN: llc < %s -mtriple=aarch64-win32-gnu | FileCheck -check-prefix=MINGW %s
define double @double() {
- ret double 0x0000000000800000
+ ret double 0x0000000000800001
}
-; CHECK: .globl __real@0000000000800000
-; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800000
+; CHECK: .globl __real@0000000000800001
+; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800001
; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: __real@0000000000800000:
-; CHECK-NEXT: .xword 8388608
+; CHECK-NEXT: __real@0000000000800001:
+; CHECK-NEXT: .xword 8388609
; CHECK: double:
-; CHECK: adrp x8, __real@0000000000800000
-; CHECK-NEXT: ldr d0, [x8, __real@0000000000800000]
+; CHECK: adrp x8, __real@0000000000800001
+; CHECK-NEXT: ldr d0, [x8, __real@0000000000800001]
; CHECK-NEXT: ret
; MINGW: .section .rdata,"dr"
; MINGW-NEXT: .p2align 3
; MINGW-NEXT: [[LABEL:\.LC.*]]:
-; MINGW-NEXT: .xword 8388608
+; MINGW-NEXT: .xword 8388609
; MINGW: double:
; MINGW: adrp x8, [[LABEL]]
; MINGW-NEXT: ldr d0, [x8, [[LABEL]]]