| commit | b4526ea132420aede87ed1bb511a03537e2f907b | [log] [tgz] |
|---|---|---|
| author | Akira Hatanaka <ahatanaka@mips.com> | Wed May 08 19:38:04 2013 +0000 |
| committer | Akira Hatanaka <ahatanaka@mips.com> | Wed May 08 19:38:04 2013 +0000 |
| tree | 2033546cacb316bc40a1775c4991f3ccc32213ab | |
| parent | 6c7a16666dbba49b9ef41c28ff7cbddf3e250213 [diff] [blame] |
[mips] Add instruction selection pattern for (seteq $LHS, 0). llvm-svn: 181459
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll new file mode 100644 index 0000000..6679536 --- /dev/null +++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -0,0 +1,11 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +; CHECK: seteq0: +; CHECK: sltiu ${{[0-9]+}}, $4, 1 + +define i32 @seteq0(i32 %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +}