commit b482e1bfe29d135dc974bb21b87f95e95dfd605a
author Jay Foad <jay.foad@amd.com> Thu Jan 23 11:51:35 2020 +0000
committer Jay Foad <jay.foad@amd.com> Thu Jan 23 13:38:13 2020 +0000
tree 3cc1beabb27dbacb4d0f25671b99de934c758580
parent d6a97b049f754f899112dc7b43a746269f7d3026

[CodeGen] Make use of MachineInstrBuilder::getReg

Reviewers: arsenm

Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73262

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 4c2dbdd..c0c865e 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -469,7 +469,7 @@
     return ValReg;
   case CCValAssign::AExt: {
     auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
-    return MIB->getOperand(0).getReg();
+    return MIB.getReg(0);
   }
   case CCValAssign::SExt: {
     Register NewReg = MRI.createGenericVirtualRegister(LocTy);