Rename MachineInstrInfo -> TargetInstrInfo
llvm-svn: 5272
diff --git a/llvm/lib/Target/Sparc/PeepholeOpts.cpp b/llvm/lib/Target/Sparc/PeepholeOpts.cpp
index f255fb7..9cff89f 100644
--- a/llvm/lib/Target/Sparc/PeepholeOpts.cpp
+++ b/llvm/lib/Target/Sparc/PeepholeOpts.cpp
@@ -9,7 +9,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
@@ -24,7 +24,7 @@
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin())
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineInstr* predMI = *(BBI-1);
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode()))
{
diff --git a/llvm/lib/Target/Sparc/PreSelection.cpp b/llvm/lib/Target/Sparc/PreSelection.cpp
index 2c3dcf2f..7cd5b1d 100644
--- a/llvm/lib/Target/Sparc/PreSelection.cpp
+++ b/llvm/lib/Target/Sparc/PreSelection.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/PreSelection.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/InstVisitor.h"
#include "llvm/Module.h"
diff --git a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
index be2cdfa..5859cb0 100644
--- a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
+++ b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
@@ -96,7 +96,7 @@
void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &MII = TM.getInstrInfo();
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock &MBB = *I;
diff --git a/llvm/lib/Target/Sparc/Sparc.cpp b/llvm/lib/Target/Sparc/Sparc.cpp
index e177910..81de95c 100644
--- a/llvm/lib/Target/Sparc/Sparc.cpp
+++ b/llvm/lib/Target/Sparc/Sparc.cpp
@@ -26,7 +26,7 @@
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
-const MachineInstrDescriptor SparcMachineInstrDesc[] = {
+const TargetInstrDescriptor SparcMachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
@@ -124,7 +124,7 @@
// Primary interface to machine description for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
// class TargetMachine, and creates machine-dependent subclasses
-// for classes such as MachineInstrInfo.
+// for classes such as TargetInstrInfo.
//
//---------------------------------------------------------------------------
diff --git a/llvm/lib/Target/Sparc/SparcInstr.def b/llvm/lib/Target/Sparc/SparcInstr.def
index 93613cb..af0fa88 100644
--- a/llvm/lib/Target/Sparc/SparcInstr.def
+++ b/llvm/lib/Target/Sparc/SparcInstr.def
@@ -35,7 +35,7 @@
// numDelaySlots (in cycles)
// latency (in cycles)
// instr sched class (defined above)
-// instr class flags (defined in MachineInstrInfo.h)
+// instr class flags (defined in TargetInstrInfo.h)
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 9891cff..df4bbc3 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -321,14 +321,14 @@
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
-// default to member functions in base class MachineInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcInstrInfo::UltraSparcInstrInfo()
- : MachineInstrInfo(SparcMachineInstrDesc,
- /*descSize = */ NUM_TOTAL_OPCODES,
- /*numRealOpCodes = */ NUM_REAL_OPCODES)
+ : TargetInstrInfo(SparcMachineInstrDesc,
+ /*descSize = */ NUM_TOTAL_OPCODES,
+ /*numRealOpCodes = */ NUM_REAL_OPCODES)
{
InitializeMaxConstantsTable();
}
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index e5eaa0f..793189a 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -41,7 +41,7 @@
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
-// const MachineInstrDescriptor SparcMachineInstrDesc[]
+// const TargetInstrDescriptor SparcMachineInstrDesc[]
//
// Purpose:
// Description of UltraSparc machine instructions.
@@ -62,7 +62,7 @@
// Array of machine instruction descriptions...
-extern const MachineInstrDescriptor SparcMachineInstrDesc[];
+extern const TargetInstrDescriptor SparcMachineInstrDesc[];
//---------------------------------------------------------------------------
@@ -72,10 +72,10 @@
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
-// default to member functions in base class MachineInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
-struct UltraSparcInstrInfo : public MachineInstrInfo {
+struct UltraSparcInstrInfo : public TargetInstrInfo {
UltraSparcInstrInfo();
//
@@ -733,7 +733,7 @@
public:
UltraSparc();
- virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
+ virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
diff --git a/llvm/lib/Target/Sparc/StackSlots.cpp b/llvm/lib/Target/Sparc/StackSlots.cpp
index 8f3a507..1ff54b9 100644
--- a/llvm/lib/Target/Sparc/StackSlots.cpp
+++ b/llvm/lib/Target/Sparc/StackSlots.cpp
@@ -8,16 +8,14 @@
#include "llvm/CodeGen/StackSlots.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Constant.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
-#include "llvm/Pass.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
namespace {
- class StackSlots : public FunctionPass {
+ class StackSlots : public MachineFunctionPass {
const TargetMachine &Target;
public:
StackSlots(const TargetMachine &T) : Target(T) {}
@@ -30,12 +28,12 @@
AU.setPreservesCFG();
}
- bool runOnFunction(Function &F) {
+ bool runOnMachineFunction(MachineFunction &MF) {
const Type *PtrInt = PointerType::get(Type::IntTy);
unsigned Size = Target.getTargetData().getTypeSize(PtrInt);
Value *V = Constant::getNullValue(Type::IntTy);
- MachineFunction::get(&F).getInfo()->allocateLocalVar(V, 2*Size);
+ MF.getInfo()->allocateLocalVar(V, 2*Size);
return true;
}
};