[AMDGPU] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Stanislav Mekhanoshin, Tom Stellard.
llvm-svn: 325425
diff --git a/llvm/test/CodeGen/AMDGPU/ret.ll b/llvm/test/CodeGen/AMDGPU/ret.ll
index d587f6a..c86cfa1 100644
--- a/llvm/test/CodeGen/AMDGPU/ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/ret.ll
@@ -126,9 +126,9 @@
; GCN-LABEL: {{^}}vgpr_ps_addr119:
; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3
-; GCN: v_mov_b32_e32 v2, v6
-; GCN: v_mov_b32_e32 v3, v8
-; GCN: v_mov_b32_e32 v4, v12
+; GCN-DAG: v_mov_b32_e32 v2, v6
+; GCN-DAG: v_mov_b32_e32 v3, v8
+; GCN-DAG: v_mov_b32_e32 v4, v12
; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 {
bb:
@@ -178,8 +178,8 @@
}
; GCN-LABEL: {{^}}sgpr:
-; GCN: s_add_i32 s0, s3, 2
; GCN: s_mov_b32 s2, s3
+; GCN: s_add_i32 s0, s2, 2
; GCN-NOT: s_endpgm
define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: