commit b58f6a4211b5bd2760ecb88df8142c167e6ef057
author Tobias Grosser <grosser@fim.uni-passau.de> Sat Jul 13 20:41:24 2013 +0000
committer Tobias Grosser <grosser@fim.uni-passau.de> Sat Jul 13 20:41:24 2013 +0000
tree d745be899d0b01e8de89b1b65bc6d0073032aa98
parent f799e3f9441c2a348af0357a61020cc1e397e66b

ScopInfo: Add getTupe() method to MemoryAccess

We also move the enum to UPPERCASE.

llvm-svn: 186259

polly/lib/Analysis/ScopInfo.cpp

diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index acb76a0..c0aeb0c 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -288,11 +288,11 @@
     // access must or may happen. However, for write accesses it is important to
     // differentiate between writes that must happen and writes that may happen.
     AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement));
-    Type = Access.isRead() ? Read : MayWrite;
+    Type = Access.isRead() ? READ : MAY_WRITE;
     return;
   }
 
-  Type = Access.isRead() ? Read : MustWrite;
+  Type = Access.isRead() ? READ : MUST_WRITE;
 
   isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset());
 
@@ -325,7 +325,7 @@
 MemoryAccess::MemoryAccess(const Value *BaseAddress, ScopStmt *Statement) {
   newAccessRelation = NULL;
   BaseAddr = BaseAddress;
-  Type = Read;
+  Type = READ;
   statement = Statement;
 
   isl_basic_map *BasicAccessMap = createBasicAccessMap(Statement);
@@ -336,13 +336,13 @@
 
 void MemoryAccess::print(raw_ostream &OS) const {
   switch (Type) {
-  case Read:
+  case READ:
     OS.indent(12) << "ReadAccess := \n";
     break;
-  case MustWrite:
+  case MUST_WRITE:
     OS.indent(12) << "MustWriteAccess := \n";
     break;
-  case MayWrite:
+  case MAY_WRITE:
     OS.indent(12) << "MayWriteAccess := \n";
     break;
   }