commit b5dff9ab50d2011ada8ec549755fb34a1a1fb63e
author Matt Arsenault <Matthew.Arsenault@amd.com> Sun Jun 15 21:08:54 2014 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Sun Jun 15 21:08:54 2014 +0000
tree b778fe7f9c0ae5049a29791325b1bff4f27c6adc
parent 14d4645e46141fdc7b88a32ef355d521c9b6c405

R600: Fix assert on vector sdiv

llvm-svn: 211000

llvm/lib/Target/R600/AMDGPUISelLowering.cpp

diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
index a7e86c9..6a3ef75 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -1321,15 +1321,15 @@
   // ilt r10, r0, 0
   SDValue r10 = DAG.getSelectCC(DL,
       r0, DAG.getConstant(0, OVT),
-      DAG.getConstant(-1, MVT::i32),
-      DAG.getConstant(0, MVT::i32),
+      DAG.getConstant(-1, OVT),
+      DAG.getConstant(0, OVT),
       ISD::SETLT);
 
   // ilt r11, r1, 0
   SDValue r11 = DAG.getSelectCC(DL,
       r1, DAG.getConstant(0, OVT),
-      DAG.getConstant(-1, MVT::i32),
-      DAG.getConstant(0, MVT::i32),
+      DAG.getConstant(-1, OVT),
+      DAG.getConstant(0, OVT),
       ISD::SETLT);
 
   // iadd r0, r0, r10