ARM: use a pseudo-instruction for cmpxchg at -O0.
The fast register-allocator cannot cope with inter-block dependencies without
spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions
where any value produced within a block is dead by the end, but not for
cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded
after regalloc.
Fortunately this is at -O0 so we don't have to care about performance. This
simplifies the various axes of expansion considerably: we assume a strong
seq_cst operation and ensure ordering via the always-present DMB instructions
rather than v8 acquire/release instructions.
Should fix the 32-bit part of PR25526.
llvm-svn: 266679
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index ca3ab8a..96dee1b 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -136,6 +136,10 @@
OptLevelO3("O3",
cl::desc("Optimization level 3. Similar to clang -O3"));
+static cl::opt<unsigned>
+CodeGenOptLevel("codegen-opt-level",
+ cl::desc("Override optimization level for codegen hooks"));
+
static cl::opt<std::string>
TargetTriple("mtriple", cl::desc("Override target triple for module"));
@@ -272,6 +276,8 @@
//
static CodeGenOpt::Level GetCodeGenOptLevel() {
+ if (CodeGenOptLevel.getNumOccurrences())
+ return static_cast<CodeGenOpt::Level>(unsigned(CodeGenOptLevel));
if (OptLevelO1)
return CodeGenOpt::Less;
if (OptLevelO2)