commit b6702eaec3bc0cbf16450829f832f4ba4cc73b04
author Simon Pilgrim <llvm-dev@redking.me.uk> Mon Apr 10 16:58:07 2017 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Mon Apr 10 16:58:07 2017 +0000
tree 9effdc478b83cc18ab9020f3129d73b55fa49ab6
parent 570e35c1570a21d98f8fce9378bfdbc36482968a

[X86][MMX] Add fast-isel support for MMX non-temporal writes

Differential Revision: https://reviews.llvm.org/D31754

llvm-svn: 299852

llvm/lib/Target/X86/X86FastISel.cpp

diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index f225696..e82f43c 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -528,6 +528,7 @@
 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
                                    X86AddressMode &AM,
                                    MachineMemOperand *MMO, bool Aligned) {
+  bool HasSSE1 = Subtarget->hasSSE1();
   bool HasSSE2 = Subtarget->hasSSE2();
   bool HasSSE4A = Subtarget->hasSSE4A();
   bool HasAVX = Subtarget->hasAVX();
@@ -588,6 +589,9 @@
     } else
       Opc = X86::ST_Fp64m;
     break;
+  case MVT::x86mmx:
+    Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr;
+    break;
   case MVT::v4f32:
     if (Aligned) {
       if (IsNonTemporal)