commit b6dac89c8753e654d3dafeec398ddcd7e9b02c4b
author Thomas Lively <tlively@google.com> Fri Dec 21 06:58:15 2018 +0000
committer Thomas Lively <tlively@google.com> Fri Dec 21 06:58:15 2018 +0000
tree be0ce86aee04465b2d35eeecae9c435b9a528919
parent aae39bf92841bd22f574d5da318303f12c2058c8

[WebAssembly] Fix invalid machine instrs in -O0, verify in tests

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D55956

llvm-svn: 349889

llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index c491678..a452a00 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -139,12 +139,15 @@
     case MVT::v16i8:
     case MVT::v8i16:
     case MVT::v4i32:
-    case MVT::v2i64:
     case MVT::v4f32:
-    case MVT::v2f64:
       if (Subtarget->hasSIMD128())
         return VT;
       break;
+    case MVT::v2i64:
+    case MVT::v2f64:
+      if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs)
+        return VT;
+      break;
     default:
       break;
     }