ARM: correctly decode VFP instructions following unpredictable t2IT
When the condition code for an IT instruction is "AL" we get strange "15"
predicates on subsequent instructions. These are dealt with for most
instructions by treating them as "ARMCC::AL", but VFP takes a different path
which didn't have this code.
llvm-svn: 335594
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f21dce3..4733cf4 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -659,6 +659,8 @@
void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
unsigned CC;
CC = ITBlock.getITCC();
+ if (CC == 0xF)
+ CC = ARMCC::AL;
if (ITBlock.instrInITBlock())
ITBlock.advanceITState();
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/llvm/test/MC/Disassembler/ARM/invalid-IT-CC15.txt
index 733895d..2ab6f93 100644
--- a/llvm/test/MC/Disassembler/ARM/invalid-IT-CC15.txt
+++ b/llvm/test/MC/Disassembler/ARM/invalid-IT-CC15.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep und
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | FileCheck %s
# rdar://10841671
0xe3 0xbf
@@ -11,8 +11,8 @@
# above sequence of junk bytes and not allowing the disassembler to abort on
# printing the final instruction in this list.
#
-# ittte al
-# vldr d19, [pc, #388]
-# vsub.f64 d17, d17, d16
-# vadd.f64 d18, d18, d19
-# vldr<und> d16, [pc, #384]
+# CHECK: ittte al
+# CHECK: vldr d19, [pc, #388]
+# CHECK: vsub.f64 d17, d17, d16
+# CHECK: vadd.f64 d18, d18, d19
+# CHECK: vldr d16, [pc, #384]