commit b745e67a64e617d4f3f3e804014a4ef9775463b8
author Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sun Mar 02 09:46:56 2014 +0000
committer Venkatraman Govindaraju <venkatra@cs.wisc.edu> Sun Mar 02 09:46:56 2014 +0000
tree 8d634663f06c9b09b39882ac58acec441d2872fd
parent 5de228b28716ff0bb2f29b45e96334b535457fe7

[SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).

llvm-svn: 202628

llvm/lib/Target/Sparc/SparcCodeEmitter.cpp

diff --git a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
index 6b5e4bf..97bacf2 100644
--- a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
@@ -78,6 +78,8 @@
                                   unsigned) const;
   unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
                                       unsigned) const;
+  unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
+                                       unsigned) const;
 
   void emitWord(unsigned Word);
 
@@ -206,6 +208,12 @@
   return getMachineOpValue(MI, MO);
 }
 
+unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
+                                                       unsigned opIdx) const {
+  const MachineOperand MO = MI.getOperand(opIdx);
+  return getMachineOpValue(MI, MO);
+}
+
 unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
                                          const MachineOperand &MO) const {