commit b8276f22807a37d9e5a1721c965d2e3e1343f025
author Petar Avramovic <Petar.Avramovic@rt-rk.com> Mon Dec 17 12:31:07 2018 +0000
committer Petar Avramovic <Petar.Avramovic@rt-rk.com> Mon Dec 17 12:31:07 2018 +0000
tree af9d34215fc488d4af39d1ed2b8e91cd68ea96ba
parent 375c54fd1e8833570013d6f44e7bd09dc87d7211

[MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD

Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32.

Differential Revision: https://reviews.llvm.org/D54580

llvm-svn: 349346

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 890ef52..4492175 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1119,6 +1119,24 @@
   case TargetOpcode::G_CTTZ:
   case TargetOpcode::G_CTPOP:
     return lowerBitCount(MI, TypeIdx, Ty);
+  case G_UADDE: {
+    unsigned Res = MI.getOperand(0).getReg();
+    unsigned CarryOut = MI.getOperand(1).getReg();
+    unsigned LHS = MI.getOperand(2).getReg();
+    unsigned RHS = MI.getOperand(3).getReg();
+    unsigned CarryIn = MI.getOperand(4).getReg();
+
+    unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
+    unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
+
+    MIRBuilder.buildAdd(TmpRes, LHS, RHS);
+    MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
+    MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
+    MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
+
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 02e787f..08e5ddd 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -20,14 +20,16 @@
 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   using namespace TargetOpcode;
 
+  const LLT s1 = LLT::scalar(1);
   const LLT s32 = LLT::scalar(32);
-  const LLT s64 = LLT::scalar(64);
   const LLT p0 = LLT::pointer(0, 32);
 
   getActionDefinitionsBuilder(G_ADD)
       .legalFor({s32})
-      .minScalar(0, s32)
-      .customFor({s64});
+      .clampScalar(0, s32, s32);
+
+  getActionDefinitionsBuilder(G_UADDE)
+      .lowerFor({{s32, s1}});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForCartesianProduct({p0, s32}, {p0});
@@ -66,33 +68,6 @@
   MIRBuilder.setInstr(MI);
 
   switch (MI.getOpcode()) {
-  case G_ADD: {
-    unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
-
-    const LLT sHalf = LLT::scalar(Size / 2);
-
-    unsigned RHSLow = MRI.createGenericVirtualRegister(sHalf);
-    unsigned RHSHigh = MRI.createGenericVirtualRegister(sHalf);
-    unsigned LHSLow = MRI.createGenericVirtualRegister(sHalf);
-    unsigned LHSHigh = MRI.createGenericVirtualRegister(sHalf);
-    unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
-    unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
-    unsigned Carry = MRI.createGenericVirtualRegister(sHalf);
-    unsigned TmpResHigh = MRI.createGenericVirtualRegister(sHalf);
-
-    MIRBuilder.buildUnmerge({RHSLow, RHSHigh}, MI.getOperand(2).getReg());
-    MIRBuilder.buildUnmerge({LHSLow, LHSHigh}, MI.getOperand(1).getReg());
-
-    MIRBuilder.buildAdd(TmpResHigh, LHSHigh, RHSHigh);
-    MIRBuilder.buildAdd(ResLow, LHSLow, RHSLow);
-    MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow);
-    MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry);
-
-    MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResLow, ResHigh});
-
-    MI.eraseFromParent();
-    break;
-  }
   default:
     return false;
   }