Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index e786ebb..122d291 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -919,6 +919,9 @@
     case X86II::XOP9:
       VEX_5M = 0x9;
       break;
+    case X86II::XOPA:
+      VEX_5M = 0xA;
+      break;
     case X86II::A6:  // Bypass: Not used by VEX
     case X86II::A7:  // Bypass: Not used by VEX
     case X86II::TB:  // Bypass: Not used by VEX