[AArch64][Inline-Asm] Return the 32-bit floating point register class
when constraint "w" is used on a 32-bit operand.
This enables compiling the following code, which used to error out in
the backend:
void foo1(int a) {
asm volatile ("sqxtn h0, %s0\n" : : "w"(a):);
}
Fixes PR28633.
llvm-svn: 276344
diff --git a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
index 4d4adb1..f3f3593 100644
--- a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -246,3 +246,11 @@
; CHECK fadd v14.4s, v0.4s, v0.4s:
ret <4 x float> %1
}
+
+define void @test_constraint_w(i32 %a) {
+ ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}}
+ ; CHECK: sqxtn h0, [[SREG]]
+
+ tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a)
+ ret void
+}