[X86] Improve handling of UDIVREM8_ZEXT_HREG/SDIVREM8_SEXT_HREG to support 64-bit extensions.
If the extend type is 64-bits, emit a 32-bit -> 64-bit extend after the UDIVREM8_ZEXT_HREG/UDIVREM8_SEXT_HREG operation.
This gives a shorter encoding for the second extend in the sext case, and allows us to completely remove the second extend in the zext case.
This also adds known bit and num sign bits support for UDIVREM8_ZEXT_HREG/SDIVREM8_SEXT_HREG.
Differential Revision: https://reviews.llvm.org/D38275
llvm-svn: 316702
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 3aa3244..d1f901e 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2912,19 +2912,7 @@
if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
- if (Node->getValueType(1) == MVT::i64) {
- // It's not possible to directly movsx AH to a 64bit register, because
- // the latter needs the REX prefix, but the former can't have it.
- assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
- "Unexpected i64 sext of h-register");
- Result =
- SDValue(CurDAG->getMachineNode(
- TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
- CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
- CurDAG->getTargetConstant(X86::sub_32bit, dl,
- MVT::i32)),
- 0);
- }
+ assert(Node->getValueType(1) == MVT::i32 && "Unexpected result type!");
} else {
Result =
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 576986d..53bc6ad 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27267,6 +27267,13 @@
Known.Zero &= Known2.Zero;
break;
}
+ case X86ISD::UDIVREM8_ZEXT_HREG:
+ // TODO: Support more than just the zero extended bits?
+ if (Op.getResNo() != 1)
+ break;
+ // The remainder is zero extended.
+ Known.Zero.setBitsFrom(8);
+ break;
}
}
@@ -27346,6 +27353,12 @@
unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth+1);
return std::min(Tmp0, Tmp1);
}
+ case X86ISD::SDIVREM8_SEXT_HREG:
+ // TODO: Support more than just the sign extended bits?
+ if (Op.getResNo() != 1)
+ break;
+ // The remainder is sign extended.
+ return VTBits - 7;
}
// Fallback case.
@@ -34853,15 +34866,19 @@
EVT VT = N->getValueType(0);
EVT InVT = N0.getValueType();
- if (N0.getResNo() != 1 || InVT != MVT::i8 || VT != MVT::i32)
+ if (N0.getResNo() != 1 || InVT != MVT::i8 ||
+ !(VT == MVT::i32 || VT == MVT::i64))
return SDValue();
- SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
+ SDVTList NodeTys = DAG.getVTList(MVT::i8, MVT::i32);
auto DivRemOpcode = OpcodeN0 == ISD::SDIVREM ? X86ISD::SDIVREM8_SEXT_HREG
: X86ISD::UDIVREM8_ZEXT_HREG;
SDValue R = DAG.getNode(DivRemOpcode, SDLoc(N), NodeTys, N0.getOperand(0),
N0.getOperand(1));
DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
+ // If this was a 64-bit extend, complete it.
+ if (VT == MVT::i64)
+ return DAG.getNode(OpcodeN, SDLoc(N), VT, R.getValue(1));
return R.getValue(1);
}