commit ba553a6e0aad74d92be87ea5720719bcb2e2581f
author Zlatko Buljan <Zlatko.Buljan@imgtec.com> Mon May 09 08:07:28 2016 +0000
committer Zlatko Buljan <Zlatko.Buljan@imgtec.com> Mon May 09 08:07:28 2016 +0000
tree ff1a43684db7d8a276d30f2c81521c678d02a521
parent 63a2083be9ffcb45a8894a4b874a821855ce8f46

[mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index eeaa5ad..c77cc47 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -1552,7 +1552,8 @@
     // fallthrough
   default:
     Inst.addOperand(MCOperand::createReg(Reg));
-    if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
+    if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||
+        Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6)
       Inst.addOperand(MCOperand::createReg(Reg+1));
 
     Inst.addOperand(MCOperand::createReg(Base));