commit baca6ed65e4dfe10b6685625786790c7015a9fd3
author Dale Johannesen <dalej@apple.com> Thu Feb 12 23:24:44 2009 +0000
committer Dale Johannesen <dalej@apple.com> Thu Feb 12 23:24:44 2009 +0000
tree 36f2811b5f5bd60531b7ac439767543e76bcd4ff
parent 6b8c76a910ecbd7f5248e00b231e2749448c49db

Check in missing file.

llvm-svn: 64410

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 3922a24..42dc448 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -213,8 +213,9 @@
     Opc = Alpha::STQ;
   else
     abort();
+  DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = 
-    BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
+    BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isReg())
@@ -261,8 +262,9 @@
     Opc = Alpha::LDQ;
   else
     abort();
+  DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = 
-    BuildMI(MF, get(Opc), DestReg);
+    BuildMI(MF, DL, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
     if (MO.isReg())