commit bb8610635f384f51969376238c53595761d814bf
author Nick Lewycky <nicholas@mxc.ca> Fri Dec 10 23:14:35 2010 +0000
committer Nick Lewycky <nicholas@mxc.ca> Fri Dec 10 23:14:35 2010 +0000
tree c792bb964081d004622fc31fc5d59ae31d8e2f27
parent 546b691c734e62c7ee9a9f7d2425dac855bda9d3

Remove extraneous close parenthesis.
Fix build breakage.

llvm-svn: 121596

llvm/lib/CodeGen/RegAllocGreedy.cpp

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index e88016f..af2c55e 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -232,7 +232,7 @@
   // Check for an available register in this class.
   DEBUG({
       const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
-      dbgs() << "RegClass: " << TRC->getName() << ' ');
+      dbgs() << "RegClass: " << TRC->getName() << ' ';
     });
 
   AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);