[AArch64] Allocate the modified and used regs only once per function.
llvm-svn: 259510
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index f010c23..0b16a2c 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -88,6 +88,9 @@
const TargetRegisterInfo *TRI;
const AArch64Subtarget *Subtarget;
+ // Track which registers have been modified and used.
+ BitVector ModifiedRegs, UsedRegs;
+
// Scan the instructions looking for a load/store that can be combined
// with the current instruction into a load/store pair.
// Return the matching instruction if one is found, else MBB->end().
@@ -1015,9 +1018,8 @@
// Track which registers have been modified and used between the first insn
// and the second insn.
- BitVector ModifiedRegs, UsedRegs;
- ModifiedRegs.resize(TRI->getNumRegs());
- UsedRegs.resize(TRI->getNumRegs());
+ ModifiedRegs.reset();
+ UsedRegs.reset();
for (unsigned Count = 0; MBBI != E && Count < Limit;) {
--MBBI;
@@ -1096,9 +1098,8 @@
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
- BitVector ModifiedRegs, UsedRegs;
- ModifiedRegs.resize(TRI->getNumRegs());
- UsedRegs.resize(TRI->getNumRegs());
+ ModifiedRegs.reset();
+ UsedRegs.reset();
// Remember any instructions that read/write memory between FirstMI and MI.
SmallVector<MachineInstr *, 4> MemInsns;
@@ -1378,9 +1379,8 @@
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
- BitVector ModifiedRegs, UsedRegs;
- ModifiedRegs.resize(TRI->getNumRegs());
- UsedRegs.resize(TRI->getNumRegs());
+ ModifiedRegs.reset();
+ UsedRegs.reset();
++MBBI;
for (; MBBI != E; ++MBBI) {
MachineInstr *MI = MBBI;
@@ -1428,9 +1428,8 @@
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
- BitVector ModifiedRegs, UsedRegs;
- ModifiedRegs.resize(TRI->getNumRegs());
- UsedRegs.resize(TRI->getNumRegs());
+ ModifiedRegs.reset();
+ UsedRegs.reset();
--MBBI;
for (; MBBI != B; --MBBI) {
MachineInstr *MI = MBBI;
@@ -1784,6 +1783,12 @@
TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
TRI = Subtarget->getRegisterInfo();
+ // Resize the modified and used register bitfield trackers. We do this once
+ // per function and then clear the bitfield each time we optimize a load or
+ // store.
+ ModifiedRegs.resize(TRI->getNumRegs());
+ UsedRegs.resize(TRI->getNumRegs());
+
bool Modified = false;
bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
for (auto &MBB : Fn)