Add all codegen passes to the PassManager via TargetPassConfig.
This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging. No functionality change.
llvm-svn: 159567
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 9aa8308..486f174 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -136,22 +136,22 @@
bool ARMPassConfig::addPreISel() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
- PM->add(createGlobalMergePass(TM->getTargetLowering()));
+ addPass(createGlobalMergePass(TM->getTargetLowering()));
return false;
}
bool ARMPassConfig::addInstSelector() {
- PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
+ addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
return false;
}
bool ARMPassConfig::addPreRegAlloc() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
- PM->add(createARMLoadStoreOptimizationPass(true));
+ addPass(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
- PM->add(createMLxExpansionPass());
+ addPass(createMLxExpansionPass());
return true;
}
@@ -159,23 +159,23 @@
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) {
- PM->add(createARMLoadStoreOptimizationPass());
+ addPass(createARMLoadStoreOptimizationPass());
printAndVerify("After ARM load / store optimizer");
}
if (getARMSubtarget().hasNEON())
- PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
+ addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
}
// Expand some pseudo instructions into multiple instructions to allow
// proper scheduling.
- PM->add(createARMExpandPseudoPass());
+ addPass(createARMExpandPseudoPass());
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
addPass(IfConverterID);
}
if (getARMSubtarget().isThumb2())
- PM->add(createThumb2ITBlockPass());
+ addPass(createThumb2ITBlockPass());
return true;
}
@@ -183,13 +183,13 @@
bool ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb())
- PM->add(createThumb2SizeReductionPass());
+ addPass(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
addPass(UnpackMachineBundlesID);
}
- PM->add(createARMConstantIslandPass());
+ addPass(createARMConstantIslandPass());
return true;
}
diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
index 3b90261..54764f1 100644
--- a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
+++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
@@ -72,7 +72,7 @@
bool SPUPassConfig::addInstSelector() {
// Install an instruction selector.
- PM->add(createSPUISelDag(getSPUTargetMachine()));
+ addPass(createSPUISelDag(getSPUTargetMachine()));
return false;
}
@@ -85,9 +85,9 @@
(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
"createTCESchedulerPass");
if (schedulerCreator != NULL)
- PM->add(schedulerCreator("cellspu"));
+ addPass(schedulerCreator("cellspu"));
//align instructions with nops/lnops for dual issue
- PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
+ addPass(createSPUNopFillerPass(getSPUTargetMachine()));
return true;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 7de27f7..8572654 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -102,22 +102,22 @@
}
bool HexagonPassConfig::addInstSelector() {
- PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
- PM->add(createHexagonISelDag(getHexagonTargetMachine()));
- PM->add(createHexagonPeephole());
+ addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
+ addPass(createHexagonISelDag(getHexagonTargetMachine()));
+ addPass(createHexagonPeephole());
return false;
}
bool HexagonPassConfig::addPreRegAlloc() {
if (!DisableHardwareLoops) {
- PM->add(createHexagonHardwareLoops());
+ addPass(createHexagonHardwareLoops());
}
return false;
}
bool HexagonPassConfig::addPostRegAlloc() {
- PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
+ addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
return true;
}
@@ -130,19 +130,19 @@
bool HexagonPassConfig::addPreEmitPass() {
if (!DisableHardwareLoops) {
- PM->add(createHexagonFixupHwLoops());
+ addPass(createHexagonFixupHwLoops());
}
- PM->add(createHexagonNewValueJump());
+ addPass(createHexagonNewValueJump());
// Expand Spill code for predicate registers.
- PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
+ addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
// Split up TFRcondsets into conditional transfers.
- PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
+ addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
// Create Packets.
- PM->add(createHexagonPacketizer());
+ addPass(createHexagonPacketizer());
return false;
}
diff --git a/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp
index 62393d0..5f82f14 100644
--- a/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeTargetMachine.cpp
@@ -68,7 +68,7 @@
// Install an instruction selector pass using
// the ISelDag to gen MBlaze code.
bool MBlazePassConfig::addInstSelector() {
- PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
+ addPass(createMBlazeISelDag(getMBlazeTargetMachine()));
return false;
}
@@ -76,6 +76,6 @@
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MBlazePassConfig::addPreEmitPass() {
- PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
+ addPass(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
return true;
}
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
index 3acf96b..817001d 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -60,12 +60,12 @@
bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector.
- PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
+ addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
return false;
}
bool MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
- PM->add(createMSP430BranchSelectionPass());
+ addPass(createMSP430BranchSelectionPass());
return false;
}
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index b03baa8..dd5d35f 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -116,7 +116,7 @@
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() {
- PM->add(createMipsISelDag(getMipsTargetMachine()));
+ addPass(createMipsISelDag(getMipsTargetMachine()));
return false;
}
@@ -125,11 +125,11 @@
// print out the code after the passes.
bool MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine();
- PM->add(createMipsDelaySlotFillerPass(TM));
+ addPass(createMipsDelaySlotFillerPass(TM));
// NOTE: long branch has not been implemented for mips16.
if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
- PM->add(createMipsLongBranchPass(TM));
+ addPass(createMipsLongBranchPass(TM));
return true;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 826b1dd..433f415 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -120,11 +120,11 @@
}
bool NVPTXPassConfig::addInstSelector() {
- PM->add(createLowerAggrCopies());
- PM->add(createSplitBBatBarPass());
- PM->add(createAllocaHoisting());
- PM->add(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
- PM->add(createVectorElementizePass(getNVPTXTargetMachine()));
+ addPass(createLowerAggrCopies());
+ addPass(createSplitBBatBarPass());
+ addPass(createAllocaHoisting());
+ addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
+ addPass(createVectorElementizePass(getNVPTXTargetMachine()));
return false;
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index d7a8088..4fbff58 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -98,20 +98,20 @@
bool PPCPassConfig::addPreRegAlloc() {
if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
- PM->add(createPPCCTRLoops());
+ addPass(createPPCCTRLoops());
return false;
}
bool PPCPassConfig::addInstSelector() {
// Install an instruction selector.
- PM->add(createPPCISelDag(getPPCTargetMachine()));
+ addPass(createPPCISelDag(getPPCTargetMachine()));
return false;
}
bool PPCPassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
- PM->add(createPPCBranchSelectionPass());
+ addPass(createPPCBranchSelectionPass());
return false;
}
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 77fd2af..9ee12ed 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -60,7 +60,7 @@
}
bool SparcPassConfig::addInstSelector() {
- PM->add(createSparcISelDag(getSparcTargetMachine()));
+ addPass(createSparcISelDag(getSparcTargetMachine()));
return false;
}
@@ -68,8 +68,8 @@
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){
- PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
- PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
+ addPass(createSparcFPMoverPass(getSparcTargetMachine()));
+ addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true;
}
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index c066a56..c66a554 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -145,38 +145,38 @@
bool X86PassConfig::addInstSelector() {
// Install an instruction selector.
- PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
+ addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
// For ELF, cleanup any local-dynamic TLS accesses.
if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
- PM->add(createCleanupLocalDynamicTLSPass());
+ addPass(createCleanupLocalDynamicTLSPass());
// For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!getX86Subtarget().is64Bit())
- PM->add(createGlobalBaseRegPass());
+ addPass(createGlobalBaseRegPass());
return false;
}
bool X86PassConfig::addPreRegAlloc() {
- PM->add(createX86MaxStackAlignmentHeuristicPass());
+ addPass(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
bool X86PassConfig::addPostRegAlloc() {
- PM->add(createX86FloatingPointStackifierPass());
+ addPass(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false;
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
- PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
+ addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
- PM->add(createX86IssueVZeroUpperPass());
+ addPass(createX86IssueVZeroUpperPass());
ShouldPrint = true;
}
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index 5afd5a1..11ec86b 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -55,7 +55,7 @@
}
bool XCorePassConfig::addInstSelector() {
- PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
+ addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
return false;
}