[RISCV] Define getSetCCResultType for setting vector setCC type
To avoid trigger "No default SetCC type for vectors!" Assertion
Differential Revision: https://reviews.llvm.org/D42675
llvm-svn: 324054
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 40a9683..239a144 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -116,6 +116,13 @@
setMinimumJumpTableEntries(INT_MAX);
}
+EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+ EVT VT) const {
+ if (!VT.isVector())
+ return getPointerTy(DL);
+ return VT.changeVectorElementTypeToInteger();
+}
+
// Changes the condition code and swaps operands if necessary, so the SetCC
// operation matches one of the comparisons supported directly in the RISC-V
// ISA.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 8ee00cd..6fbe2dd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -51,6 +51,9 @@
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const override;
+ EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+ EVT VT) const override;
+
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,
diff --git a/llvm/test/CodeGen/RISCV/get-setcc-result-type.ll b/llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
new file mode 100644
index 0000000..003f3b3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+; RV32I-LABEL: getSetCCResultType:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: xor a1, a1, zero
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: sw a1, 12(a0)
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: xor a1, a1, zero
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: sw a1, 8(a0)
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: xor a1, a1, zero
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: lw a1, 0(a0)
+; RV32I-NEXT: xor a1, a1, zero
+; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: neg a1, a1
+; RV32I-NEXT: sw a1, 0(a0)
+; RV32I-NEXT: ret
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %p, align 16
+ %cmp = icmp eq <4 x i32> %0, zeroinitializer
+ %sext = sext <4 x i1> %cmp to <4 x i32>
+ store <4 x i32> %sext, <4 x i32>* %p, align 16
+ ret void
+}