Add the extended XMM registers mappings for AVX-512.
After this we should have the entire AVX-512 register set
mapping in place.
llvm-svn: 340118
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 355b90b..7a192b7 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -251,6 +251,23 @@
{codeview::RegisterId::AMD64_K5, X86::K5},
{codeview::RegisterId::AMD64_K6, X86::K6},
{codeview::RegisterId::AMD64_K7, X86::K7},
+ {codeview::RegisterId::AMD64_XMM16, X86::XMM16},
+ {codeview::RegisterId::AMD64_XMM17, X86::XMM17},
+ {codeview::RegisterId::AMD64_XMM18, X86::XMM18},
+ {codeview::RegisterId::AMD64_XMM19, X86::XMM19},
+ {codeview::RegisterId::AMD64_XMM20, X86::XMM20},
+ {codeview::RegisterId::AMD64_XMM21, X86::XMM21},
+ {codeview::RegisterId::AMD64_XMM22, X86::XMM22},
+ {codeview::RegisterId::AMD64_XMM23, X86::XMM23},
+ {codeview::RegisterId::AMD64_XMM24, X86::XMM24},
+ {codeview::RegisterId::AMD64_XMM25, X86::XMM25},
+ {codeview::RegisterId::AMD64_XMM26, X86::XMM26},
+ {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
+ {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
+ {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
+ {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
+ {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
+
};
for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));