Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
llvm-svn: 174370
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 63cc88f..61839b6 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -34,7 +34,8 @@
// expected to be created.
assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
&& MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE");
- return MachineLocation(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
+ return MachineLocation(MI->getOperand(0).getReg(),
+ MI->getOperand(1).getImm());
}
/// Try to print a floating-point register as if it belonged to a specified
@@ -90,7 +91,8 @@
StringRef Name;
StringRef Modifier;
switch (MO.getType()) {
- default: llvm_unreachable("Unexpected operand for symbolic address constraint");
+ default:
+ llvm_unreachable("Unexpected operand for symbolic address constraint");
case MachineOperand::MO_GlobalAddress:
Name = Mang->getSymbol(MO.getGlobal())->getName();