commit bcaca87d5350f86350f444a2f783d7bf05bcfbad
author Tim Northover <Tim.Northover@arm.com> Tue Feb 05 13:24:56 2013 +0000
committer Tim Northover <Tim.Northover@arm.com> Tue Feb 05 13:24:56 2013 +0000
tree b671590b8874047ca3f12646a11897f25e504bce
parent 969afbec64dceaf6100d656bd78c3ed4693ccf06

Fix formatting in AArch64 backend.

This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

llvm-svn: 174370

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 017b509..38d0e8e 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -77,10 +77,12 @@
                                          uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                          uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                              uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
+                                              const void *Decoder);
+static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
+                                              const void *Decoder);
 
 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
                                                unsigned OptionHiS,
@@ -143,11 +145,10 @@
                                           uint64_t Address,
                                           const void *Decoder);
 
-static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
-                                        llvm::MCInst &Inst,
-                                        unsigned Val,
-                                        uint64_t Address,
-                                        const void *Decoder);
+static DecodeStatus
+DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
+                    llvm::MCInst &Inst, unsigned Val,
+                    uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
                                      unsigned Val,
@@ -247,7 +248,8 @@
 }
 
 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
@@ -460,8 +462,10 @@
   }
 
   // ASR and LSR have more specific patterns so they won't get here:
-  assert(!(ImmS == 31 && !SF && Opc != BFM) && "shift should have used auto decode");
-  assert(!(ImmS == 63 && SF && Opc != BFM) && "shift should have used auto decode");
+  assert(!(ImmS == 31 && !SF && Opc != BFM)
+         && "shift should have used auto decode");
+  assert(!(ImmS == 63 && SF && Opc != BFM)
+         && "shift should have used auto decode");
 
   // Extension instructions similarly:
   if (Opc == SBFM && ImmR == 0) {