Fix broken FileCheck prefixes
llvm-svn: 209538
diff --git a/llvm/test/CodeGen/ARM64/cse.ll b/llvm/test/CodeGen/ARM64/cse.ll
index d98bfd6..bb14c89 100644
--- a/llvm/test/CodeGen/ARM64/cse.ll
+++ b/llvm/test/CodeGen/ARM64/cse.ll
@@ -13,7 +13,7 @@
; CHECK: b.ge
; CHECK: sub
; CHECK: sub
-; CHECK_NOT: sub
+; CHECK-NOT: sub
; CHECK: ret
%0 = load i32* %offset, align 4
%cmp = icmp slt i32 %0, %size
diff --git a/llvm/test/CodeGen/ARM64/csel.ll b/llvm/test/CodeGen/ARM64/csel.ll
index 98eba30..9b42858 100644
--- a/llvm/test/CodeGen/ARM64/csel.ll
+++ b/llvm/test/CodeGen/ARM64/csel.ll
@@ -79,9 +79,9 @@
entry:
; CHECK-LABEL: foo7:
; CHECK: sub
-; CHECK-next: adds
-; CHECK-next: csneg
-; CHECK-next: b
+; CHECK-NEXT: adds
+; CHECK-NEXT: csneg
+; CHECK-NEXT: b
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, -1
%sub3 = sub nsw i32 0, %sub
diff --git a/llvm/test/CodeGen/ARM64/vmul.ll b/llvm/test/CodeGen/ARM64/vmul.ll
index b6bd16a..9d08b9d 100644
--- a/llvm/test/CodeGen/ARM64/vmul.ll
+++ b/llvm/test/CodeGen/ARM64/vmul.ll
@@ -1201,35 +1201,35 @@
; Scalar FMULX
define float @fmulxs(float %a, float %b) nounwind {
; CHECK-LABEL: fmulxs:
-; CHECKNEXT: fmulx s0, s0, s1
+; CHECK-NEXT: fmulx s0, s0, s1
%fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
-; CHECKNEXT: ret
+; CHECK-NEXT: ret
ret float %fmulx.i
}
define double @fmulxd(double %a, double %b) nounwind {
; CHECK-LABEL: fmulxd:
-; CHECKNEXT: fmulx d0, d0, d1
+; CHECK-NEXT: fmulx d0, d0, d1
%fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
-; CHECKNEXT: ret
+; CHECK-NEXT: ret
ret double %fmulx.i
}
define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind {
; CHECK-LABEL: fmulxs_lane:
-; CHECKNEXT: fmulx.s s0, s0, v1[3]
+; CHECK-NEXT: fmulx.s s0, s0, v1[3]
%b = extractelement <4 x float> %vec, i32 3
%fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
-; CHECKNEXT: ret
+; CHECK-NEXT: ret
ret float %fmulx.i
}
define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind {
; CHECK-LABEL: fmulxd_lane:
-; CHECKNEXT: fmulx d0, d0, v1[1]
+; CHECK-NEXT: fmulx d0, d0, v1[1]
%b = extractelement <2 x double> %vec, i32 1
%fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
-; CHECKNEXT: ret
+; CHECK-NEXT: ret
ret double %fmulx.i
}
diff --git a/llvm/test/CodeGen/MSP430/fp.ll b/llvm/test/CodeGen/MSP430/fp.ll
index b6ba22e..2559e23 100644
--- a/llvm/test/CodeGen/MSP430/fp.ll
+++ b/llvm/test/CodeGen/MSP430/fp.ll
@@ -21,7 +21,7 @@
; does not happen anymore. Note that the only reason an ISR is used here is that
; the register allocator selects r4 first instead of fifth in a normal function.
define msp430_intrcc void @fpb_alloced() #0 {
-; CHECK_LABEL: fpb_alloced:
+; CHECK-LABEL: fpb_alloced:
; CHECK-NOT: mov.b #0, r4
; CHECK: nop
call void asm sideeffect "nop", "r"(i8 0)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
index db33927..9eda29f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
@@ -223,7 +223,7 @@
; instructions that are erased.
define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
; ZEROTHRESH-LABEL: @take_credit(
-; ZEROTHRESH-CHECK: %1 = fadd <4 x float> %a, %b
+; ZEROTHRESH: %1 = fadd <4 x float> %a, %b
%a0 = extractelement <4 x float> %a, i32 0
%b0 = extractelement <4 x float> %b, i32 0
%c0 = fadd float %a0, %b0