Split RegisterClass 'Methods' into MethodProtos and MethodBodies
llvm-svn: 22929
diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.td b/llvm/lib/Target/IA64/IA64RegisterInfo.td
index bb58f17..d636670 100644
--- a/llvm/lib/Target/IA64/IA64RegisterInfo.td
+++ b/llvm/lib/Target/IA64/IA64RegisterInfo.td
@@ -257,14 +257,19 @@
r120, r121, r122, r123, r124, r125, r126, r127,
r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
{
- let Methods = [{
-
- iterator allocation_order_begin(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_begin(MachineFunction &MF) const;
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ GRClass::iterator
+ GRClass::allocation_order_begin(MachineFunction &MF) const {
// hide registers appropriately:
return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
}
- iterator allocation_order_end(MachineFunction &MF) const {
+ GRClass::iterator
+ GRClass::allocation_order_end(MachineFunction &MF) const {
int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
// we also can't allocate registers for use as locals if they're
diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.td b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
index a775902..2b26ea1 100644
--- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
@@ -20,11 +20,17 @@
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
R16, R15, R14, R13, R31, R0, R1, LR]>
{
- let Methods = [{
- iterator allocation_order_begin(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_begin(MachineFunction &MF) const;
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ GPRCClass::iterator
+ GPRCClass::allocation_order_begin(MachineFunction &MF) const {
return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
}
- iterator allocation_order_end(MachineFunction &MF) const {
+ GPRCClass::iterator
+ GPRCClass::allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF))
return end()-4;
else
diff --git a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.td b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
index 0831548..4555b45 100644
--- a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
@@ -20,11 +20,17 @@
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
R16, R15, R14, R13, R31, R0, R1, LR]>
{
- let Methods = [{
- iterator allocation_order_begin(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_begin(MachineFunction &MF) const;
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ GPRCClass::iterator
+ GPRCClass::allocation_order_begin(MachineFunction &MF) const {
return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
}
- iterator allocation_order_end(MachineFunction &MF) const {
+ GPRCClass::iterator
+ GPRCClass::allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF))
return end()-4;
else
diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
index 515247f..b328546 100644
--- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -97,8 +97,13 @@
G0, // constant zero
G5, G6, G7 // reserved for kernel
]> {
- let Methods = [{
- iterator allocation_order_end(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ IntRegsClass::iterator
+ IntRegsClass::allocation_order_end(MachineFunction &MF) const {
+ // FIXME: These special regs should be taken out of the regclass!
return end()-10; // Don't allocate special registers
}
}];
diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td
index 6542299..471c017 100644
--- a/llvm/lib/Target/Target.td
+++ b/llvm/lib/Target/Target.td
@@ -100,9 +100,11 @@
//
list<Register> MemberList = regList;
- // Methods - This member can be used to insert arbitrary code into a generated
- // register class. The normal usage of this is to overload virtual methods.
- code Methods = [{}];
+ // MethodProtos/MethodBodies - These members can be used to insert arbitrary
+ // code into a generated register class. The normal usage of this is to
+ // overload virtual methods.
+ code MethodProtos = [{}];
+ code MethodBodies = [{}];
}
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 55352ed..63bc7bd 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -75,8 +75,12 @@
def R8 : RegisterClass<"X86", i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
- let Methods = [{
- iterator allocation_order_end(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ R16Class::iterator
+ R16Class::allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // If so, don't allocate SP or BP
else
@@ -86,8 +90,12 @@
}
def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
- let Methods = [{
- iterator allocation_order_end(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ R32Class::iterator
+ R32Class::allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // If so, don't allocate ESP or EBP
else
@@ -115,8 +123,12 @@
// for transforming FPn allocations to STn registers)
def RST : RegisterClass<"X86", f64, 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
- let Methods = [{
- iterator allocation_order_end(MachineFunction &MF) const {
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ RSTClass::iterator
+ RSTClass::allocation_order_end(MachineFunction &MF) const {
return begin();
}
}];