[mips] interAptiv based generic schedule model
This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.
Reviewers: vkalintiris, dsanders
Differential Revision: https://reviews.llvm.org/D23551
llvm-svn: 280374
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index f775a89..3f69a96 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -132,13 +132,13 @@
; GP32: lw $[[T3:[0-9]+]], 24($sp)
; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
- ; GP32: lw $[[T6:[0-9]+]], 16($sp)
+ ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; GP32: lw $[[T7:[0-9]+]], 20($sp)
- ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
- ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+ ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+ ; GP32: lw $[[T9:[0-9]+]], 16($sp)
; GP32: addu $3, $5, $[[T8]]
; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
- ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]]
+ ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
; GP32: addu $2, $4, $[[T11]]
; GP32: move $4, $[[T5]]
; GP32: move $5, $[[T1]]
@@ -154,13 +154,13 @@
; MM32: lw $[[T3:[0-9]+]], 24($sp)
; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
- ; MM32: lw $[[T6:[0-9]+]], 16($sp)
+ ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; MM32: lw $[[T7:[0-9]+]], 20($sp)
- ; MM32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
- ; MM32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
- ; MM32: addu $[[T10:[0-9]+]], $5, $[[T9]]
- ; MM32: sltu $[[T11:[0-6]+]], $[[T9]], $[[T7]]
- ; MM32: addu $[[T12:[0-6]+]], $[[T11]], $[[T6]]
+ ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+ ; MM32: lw $[[T9:[0-9]+]], 16($sp)
+ ; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]]
+ ; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]]
+ ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]]
; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
; MM32: move $4, $[[T5]]
; MM32: move $5, $[[T1]]