[mips] interAptiv based generic schedule model
This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.
Reviewers: vkalintiris, dsanders
Differential Revision: https://reviews.llvm.org/D23551
llvm-svn: 280374
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 9d4abc8..c7f89ef 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -107,11 +107,11 @@
entry:
; ALL-LABEL: or_i128:
- ; GP32: lw $[[T0:[0-9]+]], 24($sp)
; GP32: lw $[[T1:[0-9]+]], 20($sp)
; GP32: lw $[[T2:[0-9]+]], 16($sp)
; GP32: or $2, $4, $[[T2]]
; GP32: or $3, $5, $[[T1]]
+ ; GP32: lw $[[T0:[0-9]+]], 24($sp)
; GP32: or $4, $6, $[[T0]]
; GP32: lw $[[T3:[0-9]+]], 28($sp)
; GP32: or $5, $7, $[[T3]]
@@ -119,13 +119,13 @@
; GP64: or $2, $4, $6
; GP64: or $3, $5, $7
- ; MM32: lw $[[T0:[0-9]+]], 32($sp)
- ; MM32: lw $[[T1:[0-9]+]], 28($sp)
- ; MM32: lw $[[T2:[0-9]+]], 24($sp)
+ ; MM32: lw $[[T1:[0-9]+]], 20($sp)
+ ; MM32: lw $[[T2:[0-9]+]], 16($sp)
; MM32: or16 $[[T2]], $4
; MM32: or16 $[[T1]], $5
+ ; MM32: lw $[[T0:[0-9]+]], 24($sp)
; MM32: or16 $[[T0]], $6
- ; MM32: lw $[[T3:[0-9]+]], 36($sp)
+ ; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: or16 $[[T3]], $7
; MM64: or $2, $4, $6