commit bd2b610eba36ac785692ba76f44ff9c14781eef6
author Amaury de la Vieuville <amaury.dlv@gmail.com> Thu Jun 13 16:41:55 2013 +0000
committer Amaury de la Vieuville <amaury.dlv@gmail.com> Thu Jun 13 16:41:55 2013 +0000
tree 96a959bb958ba6072779a10775f1040a2bab8d96
parent 231ca2bdc3a31c65ea4197cbfc05c3d1e285eea0

ARM: fix B decoding

llvm-svn: 183914

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index a6eab33..4086f36 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2104,7 +2104,7 @@
   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
-  int imm32 = SignExtend32<24>(tmp << 1);
+  int imm32 = SignExtend32<25>(tmp << 1);
   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
                                 true, 4, Inst, Decoder))
     Inst.addOperand(MCOperand::CreateImm(imm32));