commit bd6fca14190e9693933d96361a9fef5a19fc0981
author Sanjay Patel <spatel@rotateright.com> Wed Sep 14 15:21:00 2016 +0000
committer Sanjay Patel <spatel@rotateright.com> Wed Sep 14 15:21:00 2016 +0000
tree 941a026af5476382aa96b7b6ace5534f59d4fb21
parent fa5f767a38be412f75e4b1426356263c65291ec6

getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI

llvm-svn: 281489

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9c56054..f452d62 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2942,8 +2942,8 @@
     EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
     if (VT.isVector())
       ShiftAmountTy = VT;
-    unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
-                        ExtraVT.getScalarType().getSizeInBits();
+    unsigned BitsDiff = VT.getScalarSizeInBits() -
+                        ExtraVT.getScalarSizeInBits();
     SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
     Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
                        Node->getOperand(0), ShiftCst);