commit bdaf8bfa99830bad36c9833ca6a661294fb27577
author Francis Visoiu Mistrih <francisvm@yahoo.com> Thu Dec 14 10:03:14 2017 +0000
committer Francis Visoiu Mistrih <francisvm@yahoo.com> Thu Dec 14 10:03:14 2017 +0000
tree 578d5e8ffac8947f5141e51b8ca5cff12d89fc62
parent 5df3bbf3e637b8f9175e0f96e02aab0776f1d2f1

[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.

Only debug syntax is affected.

llvm-svn: 320683

llvm/lib/CodeGen/MIRPrinter.cpp

diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index f625be3..fcf59ad 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -797,7 +797,8 @@
   case MachineOperand::MO_TargetIndex:
   case MachineOperand::MO_JumpTableIndex:
   case MachineOperand::MO_ExternalSymbol:
-  case MachineOperand::MO_GlobalAddress: {
+  case MachineOperand::MO_GlobalAddress:
+  case MachineOperand::MO_RegisterLiveOut: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -829,21 +830,6 @@
       printCustomRegMask(Op.getRegMask(), OS, TRI);
     break;
   }
-  case MachineOperand::MO_RegisterLiveOut: {
-    const uint32_t *RegMask = Op.getRegLiveOut();
-    OS << "liveout(";
-    bool IsCommaNeeded = false;
-    for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
-      if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
-        if (IsCommaNeeded)
-          OS << ", ";
-        OS << printReg(Reg, TRI);
-        IsCommaNeeded = true;
-      }
-    }
-    OS << ")";
-    break;
-  }
   case MachineOperand::MO_Metadata:
     Op.getMetadata()->printAsOperand(OS, MST);
     break;

llvm/lib/CodeGen/MachineOperand.cpp

diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 7ffdbea..009722b 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -637,9 +637,25 @@
     OS << ">";
     break;
   }
-  case MachineOperand::MO_RegisterLiveOut:
-    OS << "<regliveout>";
+  case MachineOperand::MO_RegisterLiveOut: {
+    const uint32_t *RegMask = getRegLiveOut();
+    OS << "liveout(";
+    if (!TRI) {
+      OS << "<unknown>";
+    } else {
+      bool IsCommaNeeded = false;
+      for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
+        if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
+          if (IsCommaNeeded)
+            OS << ", ";
+          OS << printReg(Reg, TRI);
+          IsCommaNeeded = true;
+        }
+      }
+    }
+    OS << ")";
     break;
+  }
   case MachineOperand::MO_Metadata:
     OS << '<';
     getMetadata()->printAsOperand(OS, MST);