PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
instructions.
llvm-svn: 73009
diff --git a/llvm/test/CodeGen/PowerPC/vec_shift.ll b/llvm/test/CodeGen/PowerPC/vec_shift.ll
new file mode 100644
index 0000000..0cc699c
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vec_shift.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
+; PR3628
+
+define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+ %shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >
+ %shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}