commit be8a42efe2f8ffa076c84262053cca5f08ed4ae1
author Simon Atanasyan <simon@atanasyan.com> Thu May 24 07:36:06 2018 +0000
committer Simon Atanasyan <simon@atanasyan.com> Thu May 24 07:36:06 2018 +0000
tree bd34f3950eaeb62e38bea082073e305b71370440
parent 478220f1fc1fbc8d962578995c415ac60f55240b

[mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFC

llvm-svn: 333162

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 942a3a8..6e8a7f7 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3565,10 +3565,15 @@
 
 void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                    const MCSubtargetInfo *STI, bool IsImmOpnd) {
-  MipsTargetStreamer &TOut = getTargetStreamer();
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+  const MCOperand &BaseRegOp = Inst.getOperand(1);
+  assert(BaseRegOp.isReg() && "expected register operand kind");
+  const MCOperand &OffsetOp = Inst.getOperand(2);
 
-  unsigned DstReg = Inst.getOperand(0).getReg();
-  unsigned BaseReg = Inst.getOperand(1).getReg();
+  MipsTargetStreamer &TOut = getTargetStreamer();
+  unsigned DstReg = DstRegOp.getReg();
+  unsigned BaseReg = BaseRegOp.getReg();
 
   const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
   int16_t DstRegClass = Desc.OpInfo[0].RegClass;
@@ -3581,8 +3586,7 @@
     // Try to use DstReg as the temporary.
     if (IsGPR && (BaseReg != DstReg)) {
       TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
-                                 Inst.getOperand(2).getImm(), DstReg, IDLoc,
-                                 STI);
+                                 OffsetOp.getImm(), DstReg, IDLoc, STI);
       return;
     }
 
@@ -3593,11 +3597,12 @@
       return;
 
     TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
-                               Inst.getOperand(2).getImm(), ATReg, IDLoc, STI);
+                               OffsetOp.getImm(), ATReg, IDLoc, STI);
     return;
   }
 
-  const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
+  assert(OffsetOp.isExpr() && "expected expression operand kind");
+  const MCExpr *ExprOffset = OffsetOp.getExpr();
   MCOperand LoOperand = MCOperand::createExpr(
       MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
   MCOperand HiOperand = MCOperand::createExpr(
@@ -3623,14 +3628,19 @@
 void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                     const MCSubtargetInfo *STI,
                                     bool IsImmOpnd) {
-  MipsTargetStreamer &TOut = getTargetStreamer();
+  const MCOperand &SrcRegOp = Inst.getOperand(0);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+  const MCOperand &BaseRegOp = Inst.getOperand(1);
+  assert(BaseRegOp.isReg() && "expected register operand kind");
+  const MCOperand &OffsetOp = Inst.getOperand(2);
 
-  unsigned SrcReg = Inst.getOperand(0).getReg();
-  unsigned BaseReg = Inst.getOperand(1).getReg();
+  MipsTargetStreamer &TOut = getTargetStreamer();
+  unsigned SrcReg = SrcRegOp.getReg();
+  unsigned BaseReg = BaseRegOp.getReg();
 
   if (IsImmOpnd) {
     TOut.emitStoreWithImmOffset(Inst.getOpcode(), SrcReg, BaseReg,
-                                Inst.getOperand(2).getImm(),
+                                OffsetOp.getImm(),
                                 [&]() { return getATReg(IDLoc); }, IDLoc, STI);
     return;
   }
@@ -3639,7 +3649,8 @@
   if (!ATReg)
     return;
 
-  const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
+  assert(OffsetOp.isExpr() && "expected expression operand kind");
+  const MCExpr *ExprOffset = OffsetOp.getExpr();
   MCOperand LoOperand = MCOperand::createExpr(
       MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
   MCOperand HiOperand = MCOperand::createExpr(