commit c075acbb54f39e7c971c34505847f59428eb0d14
author Bill Wendling <isanbard@gmail.com> Wed Jan 06 00:23:35 2010 +0000
committer Bill Wendling <isanbard@gmail.com> Wed Jan 06 00:23:35 2010 +0000
tree 930e94079c490705f09098aa85767bdd47b9d48b
parent e51136ee05aa613a09aa43d5852aabebb019696e

The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order.

llvm-svn: 92810

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 4d51f0c..1ad7919 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1129,8 +1129,8 @@
 
   // Prefer an ordering where the lower the non-zero order number, the higher
   // the preference.
-  if (LOrder && ROrder && LOrder != ROrder)
-    return LOrder < ROrder;
+  if ((LOrder || ROrder) && LOrder != ROrder)
+    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
 
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);