Fix broken CHECK lines.
llvm-svn: 199016
diff --git a/llvm/test/CodeGen/ARM/atomic-load-store.ll b/llvm/test/CodeGen/ARM/atomic-load-store.ll
index 53c7184..45a263d 100644
--- a/llvm/test/CodeGen/ARM/atomic-load-store.ll
+++ b/llvm/test/CodeGen/ARM/atomic-load-store.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO
; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
-; RUN llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
+; RUN: llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
define void @test1(i32* %ptr, i32 %val1) {
; ARM: test1
diff --git a/llvm/test/CodeGen/ARM/divmod-eabi.ll b/llvm/test/CodeGen/ARM/divmod-eabi.ll
index 7a46af1..7f72048 100644
--- a/llvm/test/CodeGen/ARM/divmod-eabi.ll
+++ b/llvm/test/CodeGen/ARM/divmod-eabi.ll
@@ -189,7 +189,7 @@
%div = sdiv i32 %a, %b
; EABI: __aeabi_idivmod
; EABI: mov [[div:r[0-9]+]], r0
-; GNU __aeabi_idiv
+; GNU: __aeabi_idiv
; GNU: mov [[sum:r[0-9]+]], r0
; DARWIN: ___divsi3
; DARWIN: mov [[sum:r[0-9]+]], r0
diff --git a/llvm/test/CodeGen/Mips/blockaddr.ll b/llvm/test/CodeGen/Mips/blockaddr.ll
index 41c5c8f..d0319ca 100644
--- a/llvm/test/CodeGen/Mips/blockaddr.ll
+++ b/llvm/test/CodeGen/Mips/blockaddr.ll
@@ -43,8 +43,8 @@
; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
; STATIC-MIPS16-1: sll ${{[0-9]+}}, $[[R1_16]], 16
; STATIC-MIPS16-2: li ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
-; STATIC-MIPS16-1 jal dummy
-; STATIC-MIPS16-2 jal dummy
+; STATIC-MIPS16-1: jal dummy
+; STATIC-MIPS16-2: jal dummy
define void @f() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/const4a.ll b/llvm/test/CodeGen/Mips/const4a.ll
index bec61cf..b4c509f 100644
--- a/llvm/test/CodeGen/Mips/const4a.ll
+++ b/llvm/test/CodeGen/Mips/const4a.ll
@@ -15,7 +15,7 @@
entry:
store i32 -559023410, i32* @i, align 4
%0 = load i32* @b, align 4
-; no-load-relax lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst
+; no-load-relax: lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst
%tobool = icmp ne i32 %0, 0
br i1 %tobool, label %if.then, label %if.else
; no-load-relax: beqz ${{[0-9]+}}, $BB0_3
diff --git a/llvm/test/CodeGen/R600/gep-address-space.ll b/llvm/test/CodeGen/R600/gep-address-space.ll
index 4ea21dd..494b815 100644
--- a/llvm/test/CodeGen/R600/gep-address-space.ll
+++ b/llvm/test/CodeGen/R600/gep-address-space.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
-; CHECK-LABEL @use_gep_address_space:
+; CHECK-LABEL: @use_gep_address_space:
; CHECK: S_ADD_I32
%p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
store i32 99, i32 addrspace(3)* %p
diff --git a/llvm/test/CodeGen/R600/lds-output-queue.ll b/llvm/test/CodeGen/R600/lds-output-queue.ll
index 63a4332..af0db0d 100644
--- a/llvm/test/CodeGen/R600/lds-output-queue.ll
+++ b/llvm/test/CodeGen/R600/lds-output-queue.ll
@@ -87,7 +87,7 @@
; CHECK-LABEL: @local_global_alias
; CHECK: LDS_READ_RET
; CHECK-NOT: ALU clause
-; CHECK MOV * T{{[0-9]\.[XYZW]}}, OQAP
+; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
%0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
diff --git a/llvm/test/CodeGen/R600/llvm.SI.tbuffer.store.ll b/llvm/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
index fa7c3ca..33f663b 100644
--- a/llvm/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
+++ b/llvm/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
-;CHECK_LABEL: @test1
+;CHECK-LABEL: @test1
;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 32, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test1(i32 %a1, i32 %vaddr) {
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
@@ -10,7 +10,7 @@
ret void
}
-;CHECK_LABEL: @test2
+;CHECK-LABEL: @test2
;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 24, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test2(i32 %a1, i32 %vaddr) {
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
@@ -20,7 +20,7 @@
ret void
}
-;CHECK_LABEL: @test3
+;CHECK-LABEL: @test3
;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 16, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test3(i32 %a1, i32 %vaddr) {
%vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
@@ -30,7 +30,7 @@
ret void
}
-;CHECK_LABEL: @test4
+;CHECK-LABEL: @test4
;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test4(i32 %vdata, i32 %vaddr) {
call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
diff --git a/llvm/test/CodeGen/R600/local-memory.ll b/llvm/test/CodeGen/R600/local-memory.ll
index 2168a3d..8db78ad 100644
--- a/llvm/test/CodeGen/R600/local-memory.ll
+++ b/llvm/test/CodeGen/R600/local-memory.ll
@@ -17,7 +17,7 @@
; CI-CHECK-NEXT: .long 32768
; EG-CHECK: LDS_WRITE
-; SI-CHECK_NOT: S_WQM_B64
+; SI-CHECK-NOT: S_WQM_B64
; SI-CHECK: DS_WRITE_B32 0
; GROUP_BARRIER must be the last instruction in a clause
diff --git a/llvm/test/CodeGen/R600/private-memory.ll b/llvm/test/CodeGen/R600/private-memory.ll
index 48a013c..848d164 100644
--- a/llvm/test/CodeGen/R600/private-memory.ll
+++ b/llvm/test/CodeGen/R600/private-memory.ll
@@ -77,7 +77,7 @@
; loads and stores should be lowered to copies, so there shouldn't be any
; MOVA instructions.
-; R600-CHECK-LABLE: @direct_loop
+; R600-CHECK-LABEL: @direct_loop
; R600-CHECK-NOT: MOVA_INT
; SI-CHECK-LABEL: @direct_loop
; SI-CHECK-NOT: V_MOVREL
diff --git a/llvm/test/CodeGen/R600/vtx-schedule.ll b/llvm/test/CodeGen/R600/vtx-schedule.ll
index 97d37ed..ce852c5 100644
--- a/llvm/test/CodeGen/R600/vtx-schedule.ll
+++ b/llvm/test/CodeGen/R600/vtx-schedule.ll
@@ -6,9 +6,9 @@
; CHECK: @test
; CHECK: Fetch clause
-; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
+; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
; CHECK: Fetch clause
-; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
+; CHECK: VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
entry:
%0 = load i32 addrspace(1)* addrspace(1)* %in0
diff --git a/llvm/test/CodeGen/SPARC/ctpop.ll b/llvm/test/CodeGen/SPARC/ctpop.ll
index 280ed29..89c95ed 100644
--- a/llvm/test/CodeGen/SPARC/ctpop.ll
+++ b/llvm/test/CodeGen/SPARC/ctpop.ll
@@ -5,7 +5,7 @@
declare i32 @llvm.ctpop.i32(i32)
; V8-LABEL: test
-; V8-NOT : popc
+; V8-NOT: popc
; V9-LABEL: test
; V9: srl %o0, 0, %o0
diff --git a/llvm/test/CodeGen/Thumb/unord.ll b/llvm/test/CodeGen/Thumb/unord.ll
index 41a002e..3cf9ebf 100644
--- a/llvm/test/CodeGen/Thumb/unord.ll
+++ b/llvm/test/CodeGen/Thumb/unord.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
define i32 @f1(float %X, float %Y) {
-; CHECK-LABEL _f1:
+; CHECK-LABEL: _f1:
; CHECK: bne
; CHECK: .data_region
; CHECK: .long ___unordsf2
@@ -11,7 +11,7 @@
}
define i32 @f2(float %X, float %Y) {
-; CHECK-LABEL _f2:
+; CHECK-LABEL: _f2:
; CHECK: beq
; CHECK: .data_region
; CHECK: .long ___unordsf2
diff --git a/llvm/test/CodeGen/Thumb2/tail-call-r9.ll b/llvm/test/CodeGen/Thumb2/tail-call-r9.ll
index 24c76c9..673aa7c 100644
--- a/llvm/test/CodeGen/Thumb2/tail-call-r9.ll
+++ b/llvm/test/CodeGen/Thumb2/tail-call-r9.ll
@@ -6,7 +6,7 @@
; the destination address. It's callee-saved in AAPCS.
define arm_aapcscc void @test(i32 %a) nounwind {
; CHECK-LABEL: test:
-; CHECK-NOT bx r9
+; CHECK-NOT: bx r9
%tmp = load void ()** @foo, align 4
tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
tail call arm_aapcscc void %tmp() nounwind
diff --git a/llvm/test/CodeGen/X86/avx512-cvt.ll b/llvm/test/CodeGen/X86/avx512-cvt.ll
index 89a69e7..1d83485 100644
--- a/llvm/test/CodeGen/X86/avx512-cvt.ll
+++ b/llvm/test/CodeGen/X86/avx512-cvt.ll
@@ -185,7 +185,7 @@
}
; CHECK-LABEL: @fptosi02
-; CHECK vcvttss2si {{.*}} encoding: [0x62
+; CHECK: vcvttss2si {{.*}} encoding: [0x62
; CHECK: ret
define i32 @fptosi02(float %a) nounwind {
%b = fptosi float %a to i32
@@ -193,7 +193,7 @@
}
; CHECK-LABEL: @fptoui02
-; CHECK vcvttss2usi {{.*}} encoding: [0x62
+; CHECK: vcvttss2usi {{.*}} encoding: [0x62
; CHECK: ret
define i32 @fptoui02(float %a) nounwind {
%b = fptoui float %a to i32
@@ -201,7 +201,7 @@
}
; CHECK-LABEL: @uitofp02
-; CHECK vcvtusi2ss
+; CHECK: vcvtusi2ss
; CHECK: ret
define float @uitofp02(i32 %a) nounwind {
%b = uitofp i32 %a to float
@@ -209,7 +209,7 @@
}
; CHECK-LABEL: @uitofp03
-; CHECK vcvtusi2sd
+; CHECK: vcvtusi2sd
; CHECK: ret
define double @uitofp03(i32 %a) nounwind {
%b = uitofp i32 %a to double
diff --git a/llvm/test/CodeGen/X86/avx512-trunc-ext.ll b/llvm/test/CodeGen/X86/avx512-trunc-ext.ll
index 9be981c..86822a6 100644
--- a/llvm/test/CodeGen/X86/avx512-trunc-ext.ll
+++ b/llvm/test/CodeGen/X86/avx512-trunc-ext.ll
@@ -18,7 +18,7 @@
; CHECK-LABEL: zext_16x8_to_16x32
-; CHECK; vpmovzxbd {{.*}}%zmm
+; CHECK: vpmovzxbd {{.*}}%zmm
; CHECK: ret
define <16 x i32> @zext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
%x = zext <16 x i8> %i to <16 x i32>
@@ -26,7 +26,7 @@
}
; CHECK-LABEL: sext_16x8_to_16x32
-; CHECK; vpmovsxbd {{.*}}%zmm
+; CHECK: vpmovsxbd {{.*}}%zmm
; CHECK: ret
define <16 x i32> @sext_16x8_to_16x32(<16 x i8> %i) nounwind readnone {
%x = sext <16 x i8> %i to <16 x i32>
@@ -35,7 +35,7 @@
; CHECK-LABEL: zext_16x16_to_16x32
-; CHECK; vpmovzxwd {{.*}}%zmm
+; CHECK: vpmovzxwd {{.*}}%zmm
; CHECK: ret
define <16 x i32> @zext_16x16_to_16x32(<16 x i16> %i) nounwind readnone {
%x = zext <16 x i16> %i to <16 x i32>
@@ -43,7 +43,7 @@
}
; CHECK-LABEL: zext_8x16_to_8x64
-; CHECK; vpmovzxwq
+; CHECK: vpmovzxwq
; CHECK: ret
define <8 x i64> @zext_8x16_to_8x64(<8 x i16> %i) nounwind readnone {
%x = zext <8 x i16> %i to <8 x i64>
@@ -132,4 +132,4 @@
define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) {
%1 = trunc <16 x i32> %x to <16 x i16>
ret <16 x i16> %1
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/X86/vec_round.ll b/llvm/test/CodeGen/X86/vec_round.ll
index baa2f58..9258f9e 100644
--- a/llvm/test/CodeGen/X86/vec_round.ll
+++ b/llvm/test/CodeGen/X86/vec_round.ll
@@ -5,7 +5,7 @@
declare void @use(<2 x double>)
; CHECK-LABEL: @test
-; CHECK callq round
+; CHECK: callq round
; Function Attrs: nounwind uwtable
define void @test() {
diff --git a/llvm/test/CodeGen/XCore/llvm-intrinsics.ll b/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
index 5650f9d..be5fd78 100644
--- a/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
+++ b/llvm/test/CodeGen/XCore/llvm-intrinsics.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
declare i8* @llvm.frameaddress(i32) nounwind readnone
declare i8* @llvm.returnaddress(i32) nounwind
@@ -141,7 +142,7 @@
; CHECKFP: ldaw r10, sp[0]
; CHECKFP: stw r4, r10[7]
; CHECKFP: stw r5, r10[6]
-; CHECKFP: stw r6, r10[5]`
+; CHECKFP: stw r6, r10[5]
; CHECKFP: stw r7, r10[4]
; CHECKFP: stw r8, r10[3]
; CHECKFP: stw r9, r10[2]