[x86] Switch some of the new consolidated vector tests to use
a bare-metal triple and have nice BB labels, etc.
No significant change here, just tidying up to have a consistent set of
OS-agnostic vector functionality here.
llvm-svn: 218854
diff --git a/llvm/test/CodeGen/X86/vector-zext.ll b/llvm/test/CodeGen/X86/vector-zext.ll
index d47417a..84df043 100644
--- a/llvm/test/CodeGen/X86/vector-zext.ll
+++ b/llvm/test/CodeGen/X86/vector-zext.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
; SSE2-LABEL: zext_8i16_to_8i32:
-; SSE2: ## BB#0: ## %entry
+; SSE2: # BB#0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
@@ -17,7 +17,7 @@
; SSE2-NEXT: retq
;
; SSSE3-LABEL: zext_8i16_to_8i32:
-; SSSE3: ## BB#0: ## %entry
+; SSSE3: # BB#0: # %entry
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
@@ -28,7 +28,7 @@
; SSSE3-NEXT: retq
;
; SSE41-LABEL: zext_8i16_to_8i32:
-; SSE41: ## BB#0: ## %entry
+; SSE41: # BB#0: # %entry
; SSE41-NEXT: pmovzxwd %xmm0, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE41-NEXT: pand %xmm1, %xmm2
@@ -38,7 +38,7 @@
; SSE41-NEXT: retq
;
; AVX1-LABEL: zext_8i16_to_8i32:
-; AVX1: ## BB#0: ## %entry
+; AVX1: # BB#0: # %entry
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
@@ -46,7 +46,7 @@
; AVX1-NEXT: retq
;
; AVX2-LABEL: zext_8i16_to_8i32:
-; AVX2: ## BB#0: ## %entry
+; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpmovzxwd %xmm0, %ymm0
; AVX2-NEXT: retq
entry:
@@ -56,7 +56,7 @@
define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
; SSE2-LABEL: zext_4i32_to_4i64:
-; SSE2: ## BB#0: ## %entry
+; SSE2: # BB#0: # %entry
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,1,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; SSE2-NEXT: pand %xmm3, %xmm2
@@ -66,7 +66,7 @@
; SSE2-NEXT: retq
;
; SSSE3-LABEL: zext_4i32_to_4i64:
-; SSSE3: ## BB#0: ## %entry
+; SSSE3: # BB#0: # %entry
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,1,0]
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; SSSE3-NEXT: pand %xmm3, %xmm2
@@ -76,7 +76,7 @@
; SSSE3-NEXT: retq
;
; SSE41-LABEL: zext_4i32_to_4i64:
-; SSE41: ## BB#0: ## %entry
+; SSE41: # BB#0: # %entry
; SSE41-NEXT: pmovzxdq %xmm0, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; SSE41-NEXT: pand %xmm3, %xmm2
@@ -86,7 +86,7 @@
; SSE41-NEXT: retq
;
; AVX1-LABEL: zext_4i32_to_4i64:
-; AVX1: ## BB#0: ## %entry
+; AVX1: # BB#0: # %entry
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
@@ -94,7 +94,7 @@
; AVX1-NEXT: retq
;
; AVX2-LABEL: zext_4i32_to_4i64:
-; AVX2: ## BB#0: ## %entry
+; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpmovzxdq %xmm0, %ymm0
; AVX2-NEXT: retq
entry:
@@ -104,7 +104,7 @@
define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
; SSE2-LABEL: zext_8i8_to_8i32:
-; SSE2: ## BB#0: ## %entry
+; SSE2: # BB#0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
@@ -115,7 +115,7 @@
; SSE2-NEXT: retq
;
; SSSE3-LABEL: zext_8i8_to_8i32:
-; SSSE3: ## BB#0: ## %entry
+; SSSE3: # BB#0: # %entry
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
@@ -126,7 +126,7 @@
; SSSE3-NEXT: retq
;
; SSE41-LABEL: zext_8i8_to_8i32:
-; SSE41: ## BB#0: ## %entry
+; SSE41: # BB#0: # %entry
; SSE41-NEXT: pmovzxwd %xmm0, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
; SSE41-NEXT: pand %xmm1, %xmm2
@@ -136,17 +136,17 @@
; SSE41-NEXT: retq
;
; AVX1-LABEL: zext_8i8_to_8i32:
-; AVX1: ## BB#0: ## %entry
+; AVX1: # BB#0: # %entry
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]
; AVX1-NEXT: vpmovzxwd %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: vandps LCPI2_0(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vandps .{{.*}}, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: zext_8i8_to_8i32:
-; AVX2: ## BB#0: ## %entry
+; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpmovzxwd %xmm0, %ymm0
-; AVX2-NEXT: vpbroadcastd LCPI2_0(%rip), %ymm1
+; AVX2-NEXT: vpbroadcastd .{{.*}}, %ymm1
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
entry:
@@ -157,7 +157,7 @@
; PR17654
define <16 x i16> @zext_16i8_to_16i16(<16 x i8> %z) {
; SSE2-LABEL: zext_16i8_to_16i16:
-; SSE2: ## BB#0: ## %entry
+; SSE2: # BB#0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
@@ -168,7 +168,7 @@
; SSE2-NEXT: retq
;
; SSSE3-LABEL: zext_16i8_to_16i16:
-; SSSE3: ## BB#0: ## %entry
+; SSSE3: # BB#0: # %entry
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
@@ -179,7 +179,7 @@
; SSSE3-NEXT: retq
;
; SSE41-LABEL: zext_16i8_to_16i16:
-; SSE41: ## BB#0: ## %entry
+; SSE41: # BB#0: # %entry
; SSE41-NEXT: pmovzxbw %xmm0, %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
; SSE41-NEXT: pand %xmm1, %xmm2
@@ -189,7 +189,7 @@
; SSE41-NEXT: retq
;
; AVX1-LABEL: zext_16i8_to_16i16:
-; AVX1: ## BB#0: ## %entry
+; AVX1: # BB#0: # %entry
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
@@ -197,7 +197,7 @@
; AVX1-NEXT: retq
;
; AVX2-LABEL: zext_16i8_to_16i16:
-; AVX2: ## BB#0: ## %entry
+; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpmovzxbw %xmm0, %ymm0
; AVX2-NEXT: retq
entry: