commit c20b46da2f48a76f2c2affb290d8073e9ce2aab4
author Craig Topper <craig.topper@intel.com> Sun Oct 01 23:53:53 2017 +0000
committer Craig Topper <craig.topper@intel.com> Sun Oct 01 23:53:53 2017 +0000
tree eb6efb01957b9f774438ba0671e62d0fa845baa3
parent 00230604d399003acc2ac13c044535ae6b7768ee

[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem

Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.

For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.

I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995.

Reviewers: aymanmus, RKSimon, zvi

Reviewed By: aymanmus

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38120

llvm-svn: 314639

llvm/lib/Target/X86/X86InstrArithmetic.td

diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 26771e0..95f9e84 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -652,9 +652,8 @@
 
 // BinOpRR - Instructions like "add reg, reg, reg".
 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-              dag outlist, list<dag> pattern, InstrItinClass itin,
-              Format f = MRMDestReg>
-  : ITy<opcode, f, typeinfo, outlist,
+              dag outlist, list<dag> pattern, InstrItinClass itin>
+  : ITy<opcode, MRMDestReg, typeinfo, outlist,
         (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
         mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
     Sched<[WriteALU]>;
@@ -662,11 +661,11 @@
 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
 // just a EFLAGS as a result.
 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-                SDPatternOperator opnode, Format f = MRMDestReg>
+                SDPatternOperator opnode>
   : BinOpRR<opcode, mnemonic, typeinfo, (outs),
             [(set EFLAGS,
                   (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
-            IIC_BIN_NONMEM, f>;
+            IIC_BIN_NONMEM>;
 
 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
 // both a regclass and EFLAGS as a result.
@@ -727,7 +726,7 @@
 
 // BinOpRM_F - Instructions like "cmp reg, [mem]".
 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-              SDPatternOperator opnode>
+                SDNode opnode>
   : BinOpRM<opcode, mnemonic, typeinfo, (outs),
             [(set EFLAGS,
             (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
@@ -837,7 +836,7 @@
 
 // BinOpMR_F - Instructions like "cmp [mem], reg".
 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
-                  SDNode opnode>
+                SDPatternOperator opnode>
   : BinOpMR<opcode, mnemonic, typeinfo,
             [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
 
@@ -1224,10 +1223,10 @@
       def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>;
     } // isCommutable
 
-    def TEST8rm    : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
-    def TEST16rm   : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
-    def TEST32rm   : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
-    def TEST64rm   : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
+    def TEST8mr    : BinOpMR_F<0x84, "test", Xi8 , X86testpat>;
+    def TEST16mr   : BinOpMR_F<0x84, "test", Xi16, X86testpat>;
+    def TEST32mr   : BinOpMR_F<0x84, "test", Xi32, X86testpat>;
+    def TEST64mr   : BinOpMR_F<0x84, "test", Xi64, X86testpat>;
 
     def TEST8ri    : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
     def TEST16ri   : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;