[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.
For the register®ister form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register®ister form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.
I believe this supercedes D38025 which was trying to switch the register®ister form back to pre-PR22995.
Reviewers: aymanmus, RKSimon, zvi
Reviewed By: aymanmus
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38120
llvm-svn: 314639
diff --git a/llvm/test/CodeGen/X86/absolute-bit-mask.ll b/llvm/test/CodeGen/X86/absolute-bit-mask.ll
index 6e11949..818952d 100644
--- a/llvm/test/CodeGen/X86/absolute-bit-mask.ll
+++ b/llvm/test/CodeGen/X86/absolute-bit-mask.ll
@@ -43,7 +43,7 @@
define void @foo64(i64* %ptr) {
%load = load i64, i64* %ptr
; CHECK: movabsq $bit_mask64, %rax
- ; CHECK: testq (%rdi), %rax
+ ; CHECK: testq %rax, (%rdi)
%and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64)
%icmp = icmp eq i64 %and, 0
br i1 %icmp, label %t, label %f
diff --git a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
index efc384d..ee07571 100644
--- a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
+++ b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
@@ -292,7 +292,7 @@
%rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags
%rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags
%rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8)
- TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4)
+ TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4)
JNE_1 %bb.2, implicit %eflags
JMP_1 %bb.3
diff --git a/llvm/test/CodeGen/X86/testl-commute.ll b/llvm/test/CodeGen/X86/testl-commute.ll
index a9a9e58..43e095a 100644
--- a/llvm/test/CodeGen/X86/testl-commute.ll
+++ b/llvm/test/CodeGen/X86/testl-commute.ll
@@ -9,7 +9,7 @@
define i32 @test(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
@@ -30,7 +30,7 @@
define i32 @test2(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test2:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
@@ -51,7 +51,7 @@
define i32 @test3(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test3:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
diff --git a/llvm/test/MC/Disassembler/X86/x86-16.txt b/llvm/test/MC/Disassembler/X86/x86-16.txt
index 407b695..4099ea6 100644
--- a/llvm/test/MC/Disassembler/X86/x86-16.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -318,10 +318,10 @@
# CHECK: sysretl
0x0f 0x07
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
0x67 0x66 0x85 0x4d 0xe8
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
0x67 0x66 0x85 0x4d 0xe8
# CHECK: pushw %cs
diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s
index 21bec91..5e11867 100644
--- a/llvm/test/MC/X86/intel-syntax.s
+++ b/llvm/test/MC/X86/intel-syntax.s
@@ -532,14 +532,14 @@
xchg AX, [ECX]
xchg [ECX], AX
-// CHECK: testq (%ecx), %rax
-// CHECK: testq (%ecx), %rax
-// CHECK: testl (%ecx), %eax
-// CHECK: testl (%ecx), %eax
-// CHECK: testw (%ecx), %ax
-// CHECK: testw (%ecx), %ax
-// CHECK: testb (%ecx), %al
-// CHECK: testb (%ecx), %al
+// CHECK: testq %rax, (%ecx)
+// CHECK: testq %rax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testb %al, (%ecx)
+// CHECK: testb %al, (%ecx)
test RAX, [ECX]
test [ECX], RAX
test EAX, [ECX]
diff --git a/llvm/test/MC/X86/x86-16.s b/llvm/test/MC/X86/x86-16.s
index b95f66e..5ab1f23 100644
--- a/llvm/test/MC/X86/x86-16.s
+++ b/llvm/test/MC/X86/x86-16.s
@@ -406,9 +406,9 @@
// CHECK: encoding: [0x0f,0x07]
testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
push %cs
diff --git a/llvm/test/MC/X86/x86-32.s b/llvm/test/MC/X86/x86-32.s
index f3633dc..6cba31a 100644
--- a/llvm/test/MC/X86/x86-32.s
+++ b/llvm/test/MC/X86/x86-32.s
@@ -528,9 +528,9 @@
// rdar://8018260
testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
// rdar://8407242