[RISCV] Fix a couple of tests' CHECKs
llvm-svn: 370466
diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index 3940336..c5aa854 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -182,6 +182,13 @@
; RV32I-NEXT: add a0, a0, zero
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_z_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, zero
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 0)
ret i32 %1
}
@@ -194,6 +201,14 @@
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_z_nonzero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 1)
ret i32 %1
}
@@ -205,6 +220,13 @@
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_i_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
ret i32 %1
}
@@ -216,6 +238,13 @@
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_i_reg:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
ret i32 %1
}