commit c2bc2d106b5c8c99c3f0640e5dc459900ff1113f
author Manman Ren <mren@apple.com> Thu Jun 14 05:57:42 2012 +0000
committer Manman Ren <mren@apple.com> Thu Jun 14 05:57:42 2012 +0000
tree 28852001fc02a94a0e2fc8fbaed50bb56330894c
parent 596e475725971e19503f123aa8e3db2f4f933b3e

InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).

uno && ueq was converted to ueq, it should be converted to uno.

llvm-svn: 158441

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 3bafc66..7d0af0d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -995,9 +995,11 @@
       std::swap(Op0Ordered, Op1Ordered);
     }
     if (Op0Pred == 0) {
-      // uno && ueq -> uno && (uno || eq) -> ueq
+      // uno && ueq -> uno && (uno || eq) -> uno
       // ord && olt -> ord && (ord && lt) -> olt
-      if (Op0Ordered == Op1Ordered)
+      if (!Op0Ordered && (Op0Ordered == Op1Ordered))
+        return LHS;
+      if (Op0Ordered && (Op0Ordered == Op1Ordered))
         return RHS;
       
       // uno && oeq -> uno && (ord && eq) -> false