InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).
uno && ueq was converted to ueq, it should be converted to uno.
llvm-svn: 158441
diff --git a/llvm/test/CodeGen/ARM/iabs.ll b/llvm/test/CodeGen/ARM/iabs.ll
index 89e309d..e702679 100644
--- a/llvm/test/CodeGen/ARM/iabs.ll
+++ b/llvm/test/CodeGen/ARM/iabs.ll
@@ -10,7 +10,25 @@
%b = icmp sgt i32 %a, -1
%abs = select i1 %b, i32 %a, i32 %tmp1neg
ret i32 %abs
-; CHECK: movs r0, r0
+; CHECK: cmp
; CHECK: rsbmi r0, r0, #0
; CHECK: bx lr
}
+
+; rdar://11633193
+; 3 instructions will be generated for the following case:
+; subs
+; rsbmi
+; bx
+define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: test2
+; CHECK-NEXT: subs
+; CHECK-NEXT: rsbmi
+; CHECK-NEXT: bx
+ %sub = sub nsw i32 %a, %b
+ %cmp = icmp sgt i32 %sub, -1
+ %sub1 = sub nsw i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll
index 282e88b..838c2f7 100644
--- a/llvm/test/Transforms/InstCombine/and-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll
@@ -66,3 +66,14 @@
; CHECK: t6
; CHECK: ret i8 0
}
+
+define zeroext i8 @t7(float %x, float %y) nounwind {
+ %a = fcmp uno float %x, %y
+ %b = fcmp ult float %x, %y
+ %c = and i1 %a, %b
+ %retval = zext i1 %c to i8
+ ret i8 %retval
+; CHECK: t7
+; CHECK: fcmp uno
+; CHECK-NOT: fcmp ult
+}