add FCPYS and FCPYD
llvm-svn: 30995
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 099b499..e427050 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -212,6 +212,11 @@
"fcmpd $a, $b",
[(armcmp DFPRegs:$a, DFPRegs:$b)]>;
+// Floating Point Copy
+def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
+
+def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
+
// Floating Point Conversion
// We use bitconvert for moving the data between the register classes.
// The format conversion is done with ARM specific nodes
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index fd04f5a..7039523 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -47,9 +47,17 @@
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
- .addImm(ARMShift::LSL);
+ assert(RC == ARM::IntRegsRegisterClass ||
+ RC == ARM::FPRegsRegisterClass ||
+ RC == ARM::DFPRegsRegisterClass);
+
+ if (RC == ARM::IntRegsRegisterClass)
+ BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
+ .addImm(ARMShift::LSL);
+ else if (RC == ARM::FPRegsRegisterClass)
+ BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
+ else
+ BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,