Change the default scheduler from Latency to ILP, since Latency
is going away.
llvm-svn: 142810
diff --git a/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll b/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll
index 07fc10c..5425bdf 100644
--- a/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll
+++ b/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll
@@ -6,8 +6,8 @@
volatile store i32 2, i32* %x, align 4
%0 = volatile load i32* %x, align 4 ; <i32> [#uses=1]
; CHECK: lui $3, %hi($JTI0_0)
-; CHECK: sll $2, $2, 2
; CHECK: addiu $3, $3, %lo($JTI0_0)
+; CHECK: sll $2, $2, 2
switch i32 %0, label %bb4 [
i32 0, label %bb5
i32 1, label %bb1
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index 7851ba9..acd55b2 100755
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -4,8 +4,8 @@
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
+; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
@@ -18,8 +18,8 @@
@d = global i32 0, align 4
; CHECK: cmov2:
-; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
+; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}}
define i32 @cmov2(i32 %s) nounwind readonly {
entry:
diff --git a/llvm/test/CodeGen/Mips/eh.ll b/llvm/test/CodeGen/Mips/eh.ll
index 9cd3413..e3e336b 100644
--- a/llvm/test/CodeGen/Mips/eh.ll
+++ b/llvm/test/CodeGen/Mips/eh.ll
@@ -10,15 +10,11 @@
; CHECK-EL: .cfi_def_cfa_offset
; CHECK-EL: sdc1 $f20
; CHECK-EL: sw $ra
-; CHECK-EL: sw $17
-; CHECK-EL: sw $16
; CHECK-EL: .cfi_offset 52, -8
; CHECK-EL: .cfi_offset 53, -4
; CHECK-EB: .cfi_offset 53, -8
; CHECK-EB: .cfi_offset 52, -4
; CHECK-EL: .cfi_offset 31, -12
-; CHECK-EL: .cfi_offset 17, -16
-; CHECK-EL: .cfi_offset 16, -20
; CHECK-EL: .cprestore
%exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
diff --git a/llvm/test/CodeGen/Mips/fcopysign.ll b/llvm/test/CodeGen/Mips/fcopysign.ll
index 79f956d..ae49e70 100644
--- a/llvm/test/CodeGen/Mips/fcopysign.ll
+++ b/llvm/test/CodeGen/Mips/fcopysign.ll
@@ -4,27 +4,27 @@
define double @func0(double %d0, double %d1) nounwind readnone {
entry:
; CHECK-EL: func0:
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
-; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
-; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
+; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
+; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
+; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
; CHECK-EL: mtc1 $[[LO0]], $f0
; CHECK-EL: mtc1 $[[OR]], $f1
;
-; CHECK-EB: lui $[[T0:[0-9]+]], 32767
; CHECK-EB: lui $[[T1:[0-9]+]], 32768
-; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
-; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
+; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
+; CHECK-EB: lui $[[T0:[0-9]+]], 32767
+; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
+; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
; CHECK-EB: mtc1 $[[OR]], $f0
@@ -38,14 +38,14 @@
define float @func1(float %f0, float %f1) nounwind readnone {
entry:
; CHECK-EL: func1:
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
+; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
+; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; CHECK-EL: mtc1 $[[T4]], $f0
%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/fpcmp.ll b/llvm/test/CodeGen/Mips/fpcmp.ll
deleted file mode 100644
index 86545e3..0000000
--- a/llvm/test/CodeGen/Mips/fpcmp.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
-
-@g1 = external global i32
-
-define i32 @f(float %f0, float %f1) nounwind {
-entry:
-; CHECK-MIPS32: c.olt.s
-; CHECK-MIPS32: movt
-; CHECK-MIPS32: c.olt.s
-; CHECK-MIPS32: movt
- %cmp = fcmp olt float %f0, %f1
- %conv = zext i1 %cmp to i32
- %tmp2 = load i32* @g1, align 4
- %add = add nsw i32 %tmp2, %conv
- store i32 %add, i32* @g1, align 4
- %cond = select i1 %cmp, i32 10, i32 20
- ret i32 %cond
-}
diff --git a/llvm/test/CodeGen/Mips/i64arg.ll b/llvm/test/CodeGen/Mips/i64arg.ll
index 87cf2a6..8b1f71b 100644
--- a/llvm/test/CodeGen/Mips/i64arg.ll
+++ b/llvm/test/CodeGen/Mips/i64arg.ll
@@ -4,21 +4,21 @@
entry:
; CHECK: addu $[[R1:[0-9]+]], $zero, $5
; CHECK: addu $[[R0:[0-9]+]], $zero, $4
-; CHECK: lw $25, %call16(ff1)
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
+; CHECK: lw $25, %call16(ff1)
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 88($sp)
-; CHECK: lw $[[R3:[0-9]+]], 92($sp)
+; CHECK: lw $[[R2:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
-; CHECK: sw $[[R0]], 24($sp)
; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R0]], 24($sp)
; CHECK: lw $25, %call16(ff3)
; CHECK: addu $6, $zero, $[[R2]]
; CHECK: addu $7, $zero, $[[R3]]
diff --git a/llvm/test/CodeGen/Mips/inlineasmmemop.ll b/llvm/test/CodeGen/Mips/inlineasmmemop.ll
index b5db58a..4b31a88 100644
--- a/llvm/test/CodeGen/Mips/inlineasmmemop.ll
+++ b/llvm/test/CodeGen/Mips/inlineasmmemop.ll
@@ -8,10 +8,10 @@
; CHECK: #APP
; CHECK: sw $4, 0($[[T0]])
; CHECK: #NO_APP
-; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
; CHECK: #APP
; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
; CHECK: #NO_APP
+; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/Mips/o32_cc_byval.ll b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
index e673480..c5cbc7a 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
@@ -12,20 +12,20 @@
entry:
; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp)
; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
-; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
-; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
-; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
-; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK: sw $[[R2]], 16($sp)
-; CHECK: sw $[[R7]], 20($sp)
-; CHECK: sw $[[R3]], 24($sp)
-; CHECK: sw $[[R4]], 28($sp)
-; CHECK: sw $[[R5]], 32($sp)
+; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
+; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
+; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
+; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
+; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: sw $[[R6]], 36($sp)
-; CHECK: lw $6, %lo(f1.s1)($[[R1]])
+; CHECK: sw $[[R5]], 32($sp)
+; CHECK: sw $[[R4]], 28($sp)
+; CHECK: sw $[[R3]], 24($sp)
+; CHECK: sw $[[R7]], 20($sp)
+; CHECK: sw $[[R2]], 16($sp)
; CHECK: lw $7, 4($[[R0]])
+; CHECK: lw $6, %lo(f1.s1)($[[R1]])
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind
@@ -44,20 +44,20 @@
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: lw $4, 88($sp)
; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 72($sp)
+; CHECK: lw $[[R4:[0-9]+]], 76($sp)
; CHECK: lw $[[R2:[0-9]+]], 68($sp)
; CHECK: lh $[[R1:[0-9]+]], 66($sp)
; CHECK: lb $[[R0:[0-9]+]], 64($sp)
-; CHECK: lw $[[R3:[0-9]+]], 72($sp)
-; CHECK: lw $[[R4:[0-9]+]], 76($sp)
-; CHECK: lw $4, 88($sp)
-; CHECK: sw $[[R3]], 16($sp)
-; CHECK: sw $[[R4]], 20($sp)
-; CHECK: sw $[[R2]], 24($sp)
-; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 32($sp)
+; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R2]], 24($sp)
+; CHECK: sw $[[R4]], 20($sp)
+; CHECK: sw $[[R3]], 16($sp)
; CHECK: mfc1 $6, $f[[F0]]
%i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
@@ -81,12 +81,12 @@
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $4, 56($sp)
-; CHECK: sw $5, 60($sp)
-; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
-; CHECK: lw $[[R0:[0-9]+]], 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $5, 60($sp)
+; CHECK: sw $4, 56($sp)
; CHECK: lw $4, 56($sp)
+; CHECK: lw $[[R0:[0-9]+]], 68($sp)
; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@@ -100,14 +100,14 @@
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $5, 60($sp)
-; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $5, 60($sp)
+; CHECK: lw $4, 68($sp)
; CHECK: lw $[[R1:[0-9]+]], 88($sp)
; CHECK: lb $[[R0:[0-9]+]], 60($sp)
-; CHECK: lw $4, 68($sp)
-; CHECK: sw $[[R1]], 24($sp)
; CHECK: sw $[[R0]], 32($sp)
+; CHECK: sw $[[R1]], 24($sp)
%i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
%tmp = load i32* %i, align 4, !tbaa !0
diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll
index 433e896..6a087ba 100644
--- a/llvm/test/CodeGen/Mips/unalignedload.ll
+++ b/llvm/test/CodeGen/Mips/unalignedload.ll
@@ -9,27 +9,27 @@
define void @foo1() nounwind {
entry:
-; CHECK-EL: lw $25, %call16(foo2)
; CHECK-EL: ulhu $4, 2
+; CHECK-EL: lw $25, %call16(foo2)
; CHECK-EL: lw $[[R0:[0-9]+]], %got(s4)
; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
-; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]])
; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16
+; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]])
+; CHECK-EL: or $5, $[[R2]], $[[R3]]
; CHECK-EL: ulw $4, 0($[[R0]])
; CHECK-EL: lw $25, %call16(foo4)
-; CHECK-EL: or $5, $[[R2]], $[[R3]]
; CHECK-EB: ulhu $[[R0:[0-9]+]], 2
-; CHECK-EB: lw $25, %call16(foo2)
; CHECK-EB: sll $4, $[[R0]], 16
+; CHECK-EB: lw $25, %call16(foo2)
; CHECK-EB: lw $[[R1:[0-9]+]], %got(s4)
-; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]])
; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
-; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8
+; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]])
+; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
+; CHECK-EB: or $5, $[[R4]], $[[R5]]
; CHECK-EB: ulw $4, 0($[[R1]])
; CHECK-EB: lw $25, %call16(foo4)
-; CHECK-EB: or $5, $[[R4]], $[[R5]]
tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
tail call void @foo4(%struct.S4* byval @s4) nounwind