Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).
llvm-svn: 237245
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 49c2512..b4e0791 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -419,7 +419,7 @@
}
static bool isThumb(const MCSubtargetInfo& STI) {
- return STI.getFeatureBits()[ARM::ModeThumb];
+ return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
}
void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f14b694..9ce4247 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4539,7 +4539,7 @@
}
bool ARMBaseInstrInfo::hasNOP() const {
- return Subtarget.getFeatureBits()[ARM::HasV6KOps];
+ return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
}
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 18c5092..89aab26 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -265,8 +265,8 @@
}
// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
- const FeatureBitset &Bits = getFeatureBits();
- if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
+ uint64_t Bits = getFeatureBits();
+ if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
(Options.UnsafeFPMath || isTargetDarwin()))
UseNEONForSinglePrecisionFP = true;
}
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 7c09c7c..66be62d 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -243,40 +243,40 @@
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
- return STI.getFeatureBits()[ARM::ModeThumb];
+ return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
}
bool isThumbOne() const {
- return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
}
bool isThumbTwo() const {
- return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
}
bool hasThumb() const {
- return STI.getFeatureBits()[ARM::HasV4TOps];
+ return STI.getFeatureBits() & ARM::HasV4TOps;
}
bool hasV6Ops() const {
- return STI.getFeatureBits()[ARM::HasV6Ops];
+ return STI.getFeatureBits() & ARM::HasV6Ops;
}
bool hasV6MOps() const {
- return STI.getFeatureBits()[ARM::HasV6MOps];
+ return STI.getFeatureBits() & ARM::HasV6MOps;
}
bool hasV7Ops() const {
- return STI.getFeatureBits()[ARM::HasV7Ops];
+ return STI.getFeatureBits() & ARM::HasV7Ops;
}
bool hasV8Ops() const {
- return STI.getFeatureBits()[ARM::HasV8Ops];
+ return STI.getFeatureBits() & ARM::HasV8Ops;
}
bool hasARM() const {
- return !STI.getFeatureBits()[ARM::FeatureNoARM];
+ return !(STI.getFeatureBits() & ARM::FeatureNoARM);
}
bool hasThumb2DSP() const {
- return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
+ return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
}
bool hasD16() const {
- return STI.getFeatureBits()[ARM::FeatureD16];
+ return STI.getFeatureBits() & ARM::FeatureD16;
}
bool hasV8_1aOps() const {
- return STI.getFeatureBits()[ARM::HasV8_1aOps];
+ return STI.getFeatureBits() & ARM::HasV8_1aOps;
}
void SwitchMode() {
@@ -284,7 +284,7 @@
setAvailableFeatures(FB);
}
bool isMClass() const {
- return STI.getFeatureBits()[ARM::FeatureMClass];
+ return STI.getFeatureBits() & ARM::FeatureMClass;
}
/// @name Auto-generated Match Functions
@@ -9187,53 +9187,52 @@
// tools/clang/lib/Driver/Tools.cpp
static const struct {
const unsigned ID;
- const FeatureBitset Enabled;
- const FeatureBitset Disabled;
+ const uint64_t Enabled;
+ const uint64_t Disabled;
} FPUs[] = {
- {/* ID */ ARM::FK_VFP,
- /* Enabled */ {ARM::FeatureVFP2},
- /* Disabled */ {ARM::FeatureNEON}},
- {/* ID */ ARM::FK_VFPV2,
- /* Enabled */ {ARM::FeatureVFP2},
- /* Disabled */ {ARM::FeatureNEON}},
- {/* ID */ ARM::FK_VFPV3,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3},
- /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
- {/* ID */ ARM::FK_VFPV3_D16,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16},
- /* Disabled */ {ARM::FeatureNEON}},
- {/* ID */ ARM::FK_VFPV4,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4},
- /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
- {/* ID */ ARM::FK_VFPV4_D16,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureD16},
- /* Disabled */ {ARM::FeatureNEON}},
- {/* ID */ ARM::FK_FPV5_D16,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureFPARMv8, ARM::FeatureD16},
- /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}},
- {/* ID */ ARM::FK_FP_ARMV8,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureFPARMv8},
- /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}},
- {/* ID */ ARM::FK_NEON,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON},
- /* Disabled */ {ARM::FeatureD16}},
- {/* ID */ ARM::FK_NEON_VFPV4,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureNEON},
- /* Disabled */ {ARM::FeatureD16}},
- {/* ID */ ARM::FK_NEON_FP_ARMV8,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureFPARMv8, ARM::FeatureNEON},
- /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}},
+ {/* ID */ ARM::FK_VFP,
+ /* Enabled */ ARM::FeatureVFP2,
+ /* Disabled */ ARM::FeatureNEON},
+ {/* ID */ ARM::FK_VFPV2,
+ /* Enabled */ ARM::FeatureVFP2,
+ /* Disabled */ ARM::FeatureNEON},
+ {/* ID */ ARM::FK_VFPV3,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
+ /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
+ {/* ID */ ARM::FK_VFPV3_D16,
+ /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
+ /* Disabled */ ARM::FeatureNEON},
+ {/* ID */ ARM::FK_VFPV4,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
+ /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
+ {/* ID */ ARM::FK_VFPV4_D16,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureD16,
+ /* Disabled */ ARM::FeatureNEON},
+ {/* ID */ ARM::FK_FPV5_D16,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureFPARMv8 | ARM::FeatureD16,
+ /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
+ {/* ID */ ARM::FK_FP_ARMV8,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureFPARMv8,
+ /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
+ {/* ID */ ARM::FK_NEON,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
+ /* Disabled */ ARM::FeatureD16},
+ {/* ID */ ARM::FK_NEON_VFPV4,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureNEON,
+ /* Disabled */ ARM::FeatureD16},
+ {/* ID */ ARM::FK_NEON_FP_ARMV8,
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureFPARMv8 | ARM::FeatureNEON,
+ /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
{/* ID */ ARM::FK_CRYPTO_NEON_FP_ARMV8,
- /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
- ARM::FeatureFPARMv8, ARM::FeatureNEON,
- ARM::FeatureCrypto},
- /* Disabled */ {ARM::FeatureD16}},
- {ARM::FK_SOFTVFP, {}, {}},
+ /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
+ ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
+ /* Disabled */ ARM::FeatureD16},
+ {ARM::FK_SOFTVFP, 0, 0},
};
/// parseDirectiveFPU
@@ -9255,8 +9254,8 @@
// Need to toggle features that should be on but are off and that
// should off but are on.
- FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
- (Entry.Disabled & STI.getFeatureBits());
+ uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
+ (Entry.Disabled & STI.getFeatureBits());
setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
break;
}
@@ -9985,30 +9984,30 @@
static const struct {
const char *Name;
const unsigned ArchCheck;
- const FeatureBitset Features;
+ const uint64_t Features;
} Extensions[] = {
- { "crc", Feature_HasV8, {ARM::FeatureCRC} },
+ { "crc", Feature_HasV8, ARM::FeatureCRC },
{ "crypto", Feature_HasV8,
- {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
- { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} },
+ ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
+ { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
{ "idiv", Feature_HasV7 | Feature_IsNotMClass,
- {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
+ ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
// FIXME: iWMMXT not supported
- { "iwmmxt", Feature_None, {} },
+ { "iwmmxt", Feature_None, 0 },
// FIXME: iWMMXT2 not supported
- { "iwmmxt2", Feature_None, {} },
+ { "iwmmxt2", Feature_None, 0 },
// FIXME: Maverick not supported
- { "maverick", Feature_None, {} },
- { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
+ { "maverick", Feature_None, 0 },
+ { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
// FIXME: ARMv6-m OS Extensions feature not checked
- { "os", Feature_None, {} },
+ { "os", Feature_None, 0 },
// FIXME: Also available in ARMv6-K
- { "sec", Feature_HasV7, {ARM::FeatureTrustZone} },
- { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
+ { "sec", Feature_HasV7, ARM::FeatureTrustZone },
+ { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
// FIXME: Only available in A-class, isel not predicated
- { "virt", Feature_HasV7, {ARM::FeatureVirtualization} },
+ { "virt", Feature_HasV7, ARM::FeatureVirtualization },
// FIXME: xscale not supported
- { "xscale", Feature_None, {} },
+ { "xscale", Feature_None, 0 },
};
/// parseDirectiveArchExtension
@@ -10036,7 +10035,7 @@
if (Extension.Name != Name)
continue;
- if (Extension.Features.none())
+ if (!Extension.Features)
report_fatal_error("unsupported architectural extension: " + Name);
if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
@@ -10045,10 +10044,9 @@
return false;
}
- FeatureBitset ToggleFeatures = EnableFeature
- ? (~STI.getFeatureBits() & Extension.Features)
- : ( STI.getFeatureBits() & Extension.Features);
-
+ uint64_t ToggleFeatures = EnableFeature
+ ? (~STI.getFeatureBits() & Extension.Features)
+ : ( STI.getFeatureBits() & Extension.Features);
uint64_t Features =
ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
setAvailableFeatures(Features);
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f0de58a..4c169a8 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -435,7 +435,7 @@
raw_ostream &CS) const {
CommentStream = &CS;
- assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
+ assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
"mode!");
@@ -700,7 +700,7 @@
raw_ostream &CS) const {
CommentStream = &CS;
- assert(STI.getFeatureBits()[ARM::ModeThumb] &&
+ assert((STI.getFeatureBits() & ARM::ModeThumb) &&
"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
// We want to read exactly 2 bytes of data.
@@ -1026,10 +1026,9 @@
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- bool hasD16 = featureBits[ARM::FeatureD16];
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasD16 = featureBits & ARM::FeatureD16;
if (RegNo > 31 || (hasD16 && RegNo > 15))
return MCDisassembler::Fail;
@@ -1374,9 +1373,9 @@
break;
}
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
- if (featureBits[ARM::HasV8Ops] && (coproc != 14))
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
@@ -2152,10 +2151,9 @@
unsigned Imm = fieldFromInstruction(Insn, 9, 1);
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
- const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
-
- if (!FeatureBits[ARM::HasV8_1aOps] ||
- !FeatureBits[ARM::HasV8Ops])
+ uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
+ if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
+ (FeatureBits & ARM::HasV8Ops) == 0 )
return MCDisassembler::Fail;
// Decoder can be called from DecodeTST, which does not check the full
@@ -3321,11 +3319,10 @@
unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- bool hasMP = featureBits[ARM::FeatureMP];
- bool hasV7Ops = featureBits[ARM::HasV7Ops];
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasMP = featureBits & ARM::FeatureMP;
+ bool hasV7Ops = featureBits & ARM::HasV7Ops;
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3408,11 +3405,10 @@
imm |= (Rn << 9);
unsigned add = fieldFromInstruction(Insn, 9, 1);
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- bool hasMP = featureBits[ARM::FeatureMP];
- bool hasV7Ops = featureBits[ARM::HasV7Ops];
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasMP = featureBits & ARM::FeatureMP;
+ bool hasV7Ops = featureBits & ARM::HasV7Ops;
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3489,11 +3485,10 @@
unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= (Rn << 13);
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- bool hasMP = featureBits[ARM::FeatureMP];
- bool hasV7Ops = featureBits[ARM::HasV7Ops];
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasMP = (featureBits & ARM::FeatureMP);
+ bool hasV7Ops = (featureBits & ARM::HasV7Ops);
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3607,10 +3602,9 @@
unsigned U = fieldFromInstruction(Insn, 23, 1);
int imm = fieldFromInstruction(Insn, 0, 12);
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- bool hasV7Ops = featureBits[ARM::HasV7Ops];
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasV7Ops = (featureBits & ARM::HasV7Ops);
if (Rt == 15) {
switch (Inst.getOpcode()) {
@@ -3931,10 +3925,9 @@
if (Val == 0xA || Val == 0xB)
return MCDisassembler::Fail;
- const FeatureBitset &featureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
+ uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
@@ -4084,10 +4077,9 @@
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- const FeatureBitset &FeatureBits =
- ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
-
- if (FeatureBits[ARM::FeatureMClass]) {
+ uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
+ .getFeatureBits();
+ if (FeatureBits & ARM::FeatureMClass) {
unsigned ValLow = Val & 0xff;
// Validate the SYSm value first.
@@ -4107,7 +4099,7 @@
case 17: // basepri
case 18: // basepri_max
case 19: // faultmask
- if (!(FeatureBits[ARM::HasV7Ops]))
+ if (!(FeatureBits & ARM::HasV7Ops))
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler::Fail;
break;
@@ -4117,7 +4109,7 @@
if (Inst.getOpcode() == ARM::t2MSR_M) {
unsigned Mask = fieldFromInstruction(Val, 10, 2);
- if (!(FeatureBits[ARM::HasV7Ops])) {
+ if (!(FeatureBits & ARM::HasV7Ops)) {
// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
// unpredictable.
if (Mask != 2)
@@ -4131,7 +4123,7 @@
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
// only if the processor includes the DSP extension.
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
- (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
+ (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
S = MCDisassembler::SoftFail;
}
}
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index f525e4a..1c5a795 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -93,7 +93,7 @@
O << "\tsev";
break;
case 5:
- if (STI.getFeatureBits()[ARM::HasV8Ops]) {
+ if ((STI.getFeatureBits() & ARM::HasV8Ops)) {
O << "\tsevl";
break;
} // Fallthrough for non-v8
@@ -302,7 +302,7 @@
case ARM::t2SUBS_PC_LR: {
if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
MI->getOperand(0).getImm() == 0 &&
- STI.getFeatureBits()[ARM::FeatureVirtualization]) {
+ (STI.getFeatureBits() & ARM::FeatureVirtualization)) {
O << "\teret";
printPredicateOperand(MI, 1, STI, O);
printAnnotation(O, Annot);
@@ -695,7 +695,7 @@
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned val = MI->getOperand(OpNum).getImm();
- O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
+ O << ARM_MB::MemBOptToString(val, (STI.getFeatureBits() & ARM::HasV8Ops));
}
void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
@@ -795,14 +795,14 @@
const MCOperand &Op = MI->getOperand(OpNum);
unsigned SpecRegRBit = Op.getImm() >> 4;
unsigned Mask = Op.getImm() & 0xf;
- const FeatureBitset &FeatureBits = STI.getFeatureBits();
+ uint64_t FeatureBits = STI.getFeatureBits();
- if (FeatureBits[ARM::FeatureMClass]) {
+ if (FeatureBits & ARM::FeatureMClass) {
unsigned SYSm = Op.getImm();
unsigned Opcode = MI->getOpcode();
// For writes, handle extended mask bits if the DSP extension is present.
- if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
+ if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
switch (SYSm) {
case 0x400:
O << "apsr_g";
@@ -834,7 +834,7 @@
// Handle the basic 8-bit mask.
SYSm &= 0xff;
- if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
+ if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
// alias for MSR APSR_nzcvq.
switch (SYSm) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 3c6b957..590d72f 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -154,7 +154,7 @@
} // end anonymous namespace
unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
- bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
+ bool HasThumb2 = STI->getFeatureBits() & ARM::FeatureThumb2;
switch (Op) {
default:
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index 4e60372..4fa8c79 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -33,7 +33,7 @@
return ARM::NumTargetFixupKinds;
}
- bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
+ bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; }
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 6cbdeba..6b650f0 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -51,10 +51,10 @@
~ARMMCCodeEmitter() override {}
bool isThumb(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[ARM::ModeThumb];
+ return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
}
bool isThumb2(const MCSubtargetInfo &STI) const {
- return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
}
bool isTargetMachO(const MCSubtargetInfo &STI) const {
Triple TT(STI.getTargetTriple());
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 7ac83df..daa8af2 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -33,7 +33,7 @@
static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
+ if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
(MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
// Checks for the deprecated CP15ISB encoding:
@@ -65,7 +65,7 @@
static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
+ if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() != 8) {
Info = "applying IT instruction to more than one subsequent instruction is "
"deprecated";
@@ -77,7 +77,7 @@
static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
+ assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
@@ -94,7 +94,7 @@
static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
+ assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");