commit c3f85d73ab781601b2aababa8ef6572fa437c4ff
author Richard Sandiford <rsandifo@linux.vnet.ibm.com> Thu Jul 25 09:34:38 2013 +0000
committer Richard Sandiford <rsandifo@linux.vnet.ibm.com> Thu Jul 25 09:34:38 2013 +0000
tree ac52a080b4009d4aded9710c274a10fd1fcf8b06
parent abe2a36b7eeac46d1b9c0aabf616e68125dd329d

[SystemZ] Rework compare and branch support

Before the patch we took advantage of the fact that the compare and
branch are glued together in the selection DAG and fused them together
(where possible) while emitting them.  This seemed to work well in practice.
However, fusing the compare so early makes it harder to remove redundant
compares in cases where CC already has a suitable value.  This patch
therefore uses the peephole analyzeCompare/optimizeCompareInstr pair of
functions instead.

No behavioral change intended, but it paves the way for a later patch.

llvm-svn: 187116

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index b4e5531..1c55da4 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -1036,6 +1036,7 @@
            [(operator cls1:$R1, cls2:$R2)]> {
   let OpKey = mnemonic ## cls1;
   let OpType = "reg";
+  let isCompare = 1;
 }
 
 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -1045,25 +1046,31 @@
             [(operator cls1:$R1, cls2:$R2)]> {
   let OpKey = mnemonic ## cls1;
   let OpType = "reg";
+  let isCompare = 1;
 }
 
 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
                 RegisterOperand cls, Immediate imm>
   : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
            mnemonic#"\t$R1, $I2",
-           [(operator cls:$R1, imm:$I2)]>;
+           [(operator cls:$R1, imm:$I2)]> {
+  let isCompare = 1;
+}
 
 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
                  RegisterOperand cls, Immediate imm>
   : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
             mnemonic#"\t$R1, $I2",
-            [(operator cls:$R1, imm:$I2)]>;
+            [(operator cls:$R1, imm:$I2)]> {
+  let isCompare = 1;
+}
 
 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
                    RegisterOperand cls, SDPatternOperator load>
   : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
             mnemonic#"\t$R1, $I2",
             [(operator cls:$R1, (load pcrel32:$I2))]> {
+  let isCompare = 1;
   let mayLoad = 1;
   // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
   // However, BDXs have two extra operands and are therefore 6 units more
@@ -1079,6 +1086,7 @@
            [(operator cls:$R1, (load mode:$XBD2))]> {
   let OpKey = mnemonic ## cls;
   let OpType = "mem";
+  let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
@@ -1090,6 +1098,7 @@
             [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
   let OpKey = mnemonic ## cls;
   let OpType = "mem";
+  let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
@@ -1102,6 +1111,7 @@
             [(operator cls:$R1, (load mode:$XBD2))]> {
   let OpKey = mnemonic ## cls;
   let OpType = "mem";
+  let isCompare = 1;
   let mayLoad = 1;
   let AccessBytes = bytes;
 }
@@ -1125,6 +1135,7 @@
   : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
            mnemonic#"\t$BD1, $I2",
            [(operator (load mode:$BD1), imm:$I2)]> {
+  let isCompare = 1;
   let mayLoad = 1;
 }
 
@@ -1133,6 +1144,7 @@
   : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
+  let isCompare = 1;
   let mayLoad = 1;
 }
 
@@ -1142,6 +1154,7 @@
   : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
             mnemonic#"\t$BD1, $I2",
             [(operator (load mode:$BD1), imm:$I2)]> {
+  let isCompare = 1;
   let mayLoad = 1;
 }