Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
The regression on ppc64 was not due to this commit.
llvm-svn: 320788
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index f3017ac..6be1373 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1053,7 +1053,10 @@
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);
);
- assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
+ assert((BotRPTracker.getPos() == RegionEnd ||
+ (RegionEnd->isDebugValue() &&
+ BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
+ "Can't find the region bottom");
// Cache the list of excess pressure sets in this region. This will also track
// the max pressure in the scheduled code for these sets.
@@ -1459,7 +1462,8 @@
RegOpers.detectDeadDefs(*MI, *LIS);
}
- BotRPTracker.recedeSkipDebugValues();
+ if (BotRPTracker.getPos() != CurrentBottom)
+ BotRPTracker.recedeSkipDebugValues();
SmallVector<RegisterMaskPair, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");