commit c41e2f6e7b71530bf1b3fed95e0f67ddbba29d3f
author Yaxun Liu <Yaxun.Liu@amd.com> Fri Dec 15 03:56:57 2017 +0000
committer Yaxun Liu <Yaxun.Liu@amd.com> Fri Dec 15 03:56:57 2017 +0000
tree f61a9cfeee07ada16e54862c680ea6a73c08d7db
parent b99a7102c13bd6bf629789750d2e5c08e9862da1

Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value

The regression on ppc64 was not due to this commit.

llvm-svn: 320788

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index e9e53d5..ac4468f 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -776,7 +776,8 @@
       if (PDiffs != nullptr)
         PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
 
-      RPTracker->recedeSkipDebugValues();
+      if (RPTracker->getPos() == RegionEnd || &*RPTracker->getPos() != &MI)
+        RPTracker->recedeSkipDebugValues();
       assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
       RPTracker->recede(RegOpers);
     }